cpldfit: version M.81d Xilinx Inc. Fitter Report Design Name: CPLDfreezer Date: 12-26-2011, 6:15PM Device Used: XC9536-15-PC44 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 13 /36 ( 36%) 30 /180 ( 17%) 42 /72 ( 58%) 4 /36 ( 11%) 34 /34 (100%) ** Function Block Resources ** Function Mcells FB Inps Signals Pterms IO Block Used/Tot Used/Tot Used Used/Tot Used/Tot FB1 9/18 28/36 28 22/90 2/17 FB2 4/18 14/36 14 8/90 4/17 ----- ----- ----- ----- 13/36 42/72 30/180 6/34 * - Resource is exhausted ** Global Control Resources ** Signal 'NMI' mapped onto global clock net GCK1. Signal 'PHI_1' mapped onto global clock net GCK2. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 26 26 | I/O : 28 28 Output : 6 6 | GCK/IO : 3 3 Bidirectional : 0 0 | GTS/IO : 2 2 GCK : 2 2 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 34 34 ** Power Data ** There are 13 macrocells in high performance mode (MCHP). There are 0 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'CPLDfreezer.ise'. ************************* Summary of Mapped Logic ************************ ** 6 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State FREEZER_ROM 4 19 FB1_2 3 I/O O STD FAST OS_ROM 4 19 FB1_11 13 I/O O STD FAST CASINH_FRED_4 2 4 FB2_2 44 I/O O STD FAST RAM_RA0 2 9 FB2_8 37 I/O O STD FAST RAM_RA5 2 9 FB2_12 33 I/O O STD FAST RAM_RA7 2 9 FB2_16 26 I/O O STD FAST ** 7 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State XLXN_368/XLXN_368_CLKF__$INT 1 18 FB1_12 STD XLXN_349 1 1 FB1_13 STD RESET XLXN_368/XLXN_368_RSTF__$INT 2 4 FB1_14 STD XLXN_368 2 2 FB1_15 STD RESET XLXN_282 2 2 FB1_16 STD RESET XLXN_267 2 2 FB1_17 STD RESET XLXN_282/XLXN_282_CLKF__$INT 4 9 FB1_18 STD ** 28 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use D7xx FB1_1 2 I/O I NMI FB1_3 5~ GCK/I/O GCK A8 FB1_4 4 I/O I PHI_1 FB1_5 6~ GCK/I/O GCK/I A12 FB1_6 8 I/O I CASINH_MMU_16 FB1_7 7 GCK/I/O I A14 FB1_8 9 I/O I A15 FB1_9 11 I/O I A6 FB1_10 12 I/O I A7 FB1_12 14 I/O I A3 FB1_13 18 I/O I A10 FB1_14 19 I/O I HALT FB1_15 20 I/O I RW FB1_16 22 I/O I FRED25 FB1_17 24 I/O I FRED27 FB2_1 1 I/O I PHI_2 FB2_3 42 GTS/I/O I RESET FB2_4 43 I/O I FRED32 FB2_5 40 GTS/I/O I MMU_17 FB2_6 39 GSR/I/O I A1 FB2_7 38 I/O I A11 FB2_9 36 I/O I A13 FB2_10 35 I/O I A4 FB2_11 34 I/O I A5 FB2_13 29 I/O I A9 FB2_14 28 I/O I A0 FB2_15 27 I/O I FREEZER FB2_17 25 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X(@) - Signal used as input (wire-AND input) to the macrocell logic. The number of Signals Used may exceed the number of FB Inputs Used due to wire-ANDing in the switch matrix. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 28/8 Number of signals used by logic mapping into function block: 28 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB1_1 2 I/O I FREEZER_ROM 4 0 0 1 FB1_2 3 I/O O (unused) 0 0 0 5 FB1_3 5 GCK/I/O GCK (unused) 0 0 0 5 FB1_4 4 I/O I (unused) 0 0 0 5 FB1_5 6 GCK/I/O GCK/I (unused) 0 0 0 5 FB1_6 8 I/O I (unused) 0 0 0 5 FB1_7 7 GCK/I/O I (unused) 0 0 0 5 FB1_8 9 I/O I (unused) 0 0 0 5 FB1_9 11 I/O I (unused) 0 0 0 5 FB1_10 12 I/O I OS_ROM 4 0 0 1 FB1_11 13 I/O O XLXN_368/XLXN_368_CLKF__$INT 1 0 0 4 FB1_12 14 I/O I XLXN_349 1 0 0 4 FB1_13 18 I/O I XLXN_368/XLXN_368_RSTF__$INT 2 0 0 3 FB1_14 19 I/O I XLXN_368 2 0 0 3 FB1_15 20 I/O I XLXN_282 2 0 0 3 FB1_16 22 I/O I XLXN_267 2 0 0 3 FB1_17 24 I/O I XLXN_282/XLXN_282_CLKF__$INT 4 0 0 1 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: A0 11: A5 20: RESET 2: A10 12: A6 21: RW 3: A11 13: A7 22: XLXN_267 4: A12 14: A8 23: XLXN_282 5: A13 15: A9 24: XLXN_282/XLXN_282_CLKF__$INT 6: A14 16: D7xx 25: XLXN_349 7: A15 17: FREEZER 26: XLXN_368 8: A1 18: HALT 27: XLXN_368/XLXN_368_CLKF__$INT 9: A3 19: PHI_1 28: XLXN_368/XLXN_368_RSTF__$INT 10: A4 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs FREEZER_ROM XXXXXXXXXXXXXXX......XX.XX.............. 19 19 OS_ROM XXXXXXXXXXXXXXX......XX.XX.............. 19 19 XLXN_368/XLXN_368_CLKF__$INT XXXXXXXXXXXXXXX......X..XX.............. 18 18 XLXN_349 .................X...................... 1 1 XLXN_368/XLXN_368_RSTF__$INT ...............X..XXX................... 4 4 XLXN_368 ..........................XX............ 2 2 XLXN_282 .......................X..X............. 2 2 XLXN_267 ................X..........X............ 2 2 XLXN_282/XLXN_282_CLKF__$INT ..XXXXX........X..X.X....X.............. 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 14/22 Number of signals used by logic mapping into function block: 14 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use (unused) 0 0 0 5 FB2_1 1 I/O I CASINH_FRED_4 2 0 0 3 FB2_2 44 I/O O (unused) 0 0 0 5 FB2_3 42 GTS/I/O I (unused) 0 0 0 5 FB2_4 43 I/O I (unused) 0 0 0 5 FB2_5 40 GTS/I/O I (unused) 0 0 0 5 FB2_6 39 GSR/I/O I (unused) 0 0 0 5 FB2_7 38 I/O I RAM_RA0 2 0 0 3 FB2_8 37 I/O O (unused) 0 0 0 5 FB2_9 36 I/O I (unused) 0 0 0 5 FB2_10 35 I/O I (unused) 0 0 0 5 FB2_11 34 I/O I RAM_RA5 2 0 0 3 FB2_12 33 I/O O (unused) 0 0 0 5 FB2_13 29 I/O I (unused) 0 0 0 5 FB2_14 28 I/O I (unused) 0 0 0 5 FB2_15 27 I/O I RAM_RA7 2 0 0 3 FB2_16 26 I/O O (unused) 0 0 0 5 FB2_17 25 I/O I (unused) 0 0 0 5 FB2_18 (b) Signals Used by Logic in Function Block 1: A11 6: CASINH_MMU_16 11: PHI_2 2: A12 7: FRED25 12: RW 3: A13 8: FRED27 13: XLXN_282 4: A14 9: FRED32 14: XLXN_368 5: A15 10: MMU_17 Signal 1 2 3 4 Signals FB Name 0----+----0----+----0----+----0----+----0 Used Inputs CASINH_FRED_4 .....X...X.X.X.......................... 4 4 RAM_RA0 XXXXX...X.X.XX.......................... 9 9 RAM_RA5 XXXXX..X..X.XX.......................... 9 9 RAM_RA7 XXXXX.X...X.XX.......................... 9 9 0----+----1----+----2----+----3----+----4 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** CASINH_FRED_4 <= ((CASINH_MMU_16) OR (NOT XLXN_368 AND NOT RW AND NOT MMU_17)); FREEZER_ROM <= NOT (((A12 AND NOT A14 AND NOT A15 AND NOT XLXN_282 AND XLXN_368) OR (NOT A14 AND NOT A15 AND A13 AND NOT XLXN_282 AND XLXN_368) OR (NOT A14 AND NOT A15 AND A11 AND NOT XLXN_282 AND XLXN_368) OR (A6 AND A4 AND A1 AND A7 AND A5 AND A3 AND A12 AND A9 AND A8 AND A14 AND A10 AND A15 AND A13 AND A11 AND A0 AND NOT XLXN_282 AND XLXN_267 AND NOT XLXN_368 AND XLXN_349))); OS_ROM <= ((A12 AND NOT A14 AND NOT A15 AND NOT XLXN_282 AND XLXN_368) OR (NOT A14 AND NOT A15 AND A13 AND NOT XLXN_282 AND XLXN_368) OR (NOT A14 AND NOT A15 AND A11 AND NOT XLXN_282 AND XLXN_368) OR (A6 AND A4 AND A1 AND A7 AND A5 AND A3 AND A12 AND A9 AND A8 AND A14 AND A10 AND A15 AND A13 AND A11 AND A0 AND NOT XLXN_282 AND XLXN_267 AND NOT XLXN_368 AND XLXN_349)); RAM_RA0 <= ((FRED32) OR (NOT A12 AND NOT A14 AND NOT A15 AND NOT A13 AND NOT A11 AND NOT XLXN_282 AND PHI_2 AND XLXN_368)); RAM_RA5 <= ((FRED27) OR (NOT A12 AND NOT A14 AND NOT A15 AND NOT A13 AND NOT A11 AND NOT XLXN_282 AND PHI_2 AND XLXN_368)); RAM_RA7 <= ((FRED25) OR (NOT A12 AND NOT A14 AND NOT A15 AND NOT A13 AND NOT A11 AND NOT XLXN_282 AND PHI_2 AND XLXN_368)); FDCPE_XLXN_267: FDCPE port map (XLXN_267,NOT FREEZER,NMI,NOT XLXN_368/XLXN_368_RSTF__$INT,'0'); FTCPE_XLXN_282: FTCPE port map (XLXN_282,'1',NOT XLXN_282/XLXN_282_CLKF__$INT,NOT XLXN_368/XLXN_368_CLKF__$INT,'0'); XLXN_282/XLXN_282_CLKF__$INT <= ((A14 AND NOT PHI_1 AND NOT D7xx AND NOT RW) OR (A15 AND NOT PHI_1 AND NOT D7xx AND NOT RW) OR (NOT XLXN_368 AND NOT PHI_1 AND NOT D7xx AND NOT RW) OR (NOT A12 AND NOT A13 AND NOT A11 AND NOT PHI_1 AND NOT D7xx AND NOT RW)); FDCPE_XLXN_349: FDCPE port map (XLXN_349,HALT,PHI_1,'0','0'); FDCPE_XLXN_368: FDCPE port map (XLXN_368,'1',NOT XLXN_368/XLXN_368_CLKF__$INT,NOT XLXN_368/XLXN_368_RSTF__$INT,'0'); XLXN_368/XLXN_368_CLKF__$INT <= (A6 AND A4 AND A1 AND A7 AND A5 AND A3 AND A12 AND A9 AND A8 AND A14 AND A10 AND A15 AND A13 AND A11 AND A0 AND XLXN_267 AND NOT XLXN_368 AND XLXN_349); XLXN_368/XLXN_368_RSTF__$INT <= ((NOT RESET) OR (NOT PHI_1 AND NOT D7xx AND RW)); Register Legend: FDCPE (Q,D,C,CLR,PRE); FTCPE (Q,D,C,CLR,PRE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC9536-15-PC44 -------------------------------- /6 5 4 3 2 1 44 43 42 41 40 \ | 7 39 | | 8 38 | | 9 37 | | 10 36 | | 11 XC9536-15-PC44 35 | | 12 34 | | 13 33 | | 14 32 | | 15 31 | | 16 30 | | 17 29 | \ 18 19 20 21 22 23 24 25 26 27 28 / -------------------------------- Pin Signal Pin Signal No. Name No. Name 1 FRED27 23 GND 2 D7xx 24 FRED25 3 FREEZER_ROM 25 FREEZER 4 A8 26 RAM_RA7 5 NMI 27 A0 6 PHI_1 28 A9 7 CASINH_MMU_16 29 A5 8 A12 30 TDO 9 A14 31 GND 10 GND 32 VCC 11 A15 33 RAM_RA5 12 A6 34 A4 13 OS_ROM 35 A13 14 A7 36 A11 15 TDI 37 RAM_RA0 16 TMS 38 A1 17 TCK 39 MMU_17 18 A3 40 FRED32 19 A10 41 VCC 20 HALT 42 PHI_2 21 VCC 43 RESET 22 RW 44 CASINH_FRED_4 Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc9536-15-PC44 Optimization Method : SPEED Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : OFF Keep Unused Inputs : OFF Slew Rate : FAST Power Mode : STD Ground on Unused IOs : OFF Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON FASTConnect/UIM optimzation : ON Local Feedback : ON Pin Feedback : ON Input Limit : 36 Pterm Limit : 25