Design Name | CPLDfreezer |
Device, Speed (SpeedFile Version) | XC9536, -15 (3.0) |
Date Created | Mon Dec 26 18:15:21 2011 |
Created By | Timing Report Generator: version M.81d |
Copyright | Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. |
Notes and Warnings |
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Note: This design contains no timing constraints. |
Note: A default set of constraints using a delay of 0.000ns will be used for analysis. |
Possible asynchronous logic: Clock pin 'XLXN_368.CLKF' has multiple original clock nets 'XLXN_349.Q' 'XLXN_267.Q' 'A0' 'A10' 'A8' 'A9' 'A3' 'A5' 'A7' 'A1' 'A4' 'A6' 'A11' 'A13' 'A12' 'XLXN_368.Q' 'A15' 'A14'. |
Possible asynchronous logic: Clock pin 'XLXN_282.CLKF' has multiple original clock nets 'A11' 'A13' 'A12' 'XLXN_368.Q' 'A15' 'RW' 'D7xx' 'PHI_1' 'A14'. |
Performance Summary | |
---|---|
Min. Clock Period | 14.000 ns. |
Max. Clock Frequency (fSYSTEM) | 71.429 MHz. |
Limited by Clock Pulse Width for XLXN_349.Q | |
Pad to Pad Delay (tPD) | 15.000 ns. |
Setup to Clock at the Pad (tSU) | 8.000 ns. |
Clock Pad to Output Pad Delay (tCO) | 87.000 ns. |
Constraint Name | Requirement (ns) | Delay (ns) | Paths | Paths Failing |
---|---|---|---|---|
TS1000 | 0.0 | 0.0 | 0 | 0 |
TS1001 | 0.0 | 0.0 | 0 | 0 |
TS1002 | 0.0 | 0.0 | 0 | 0 |
TS1003 | 0.0 | 0.0 | 0 | 0 |
TS1004 | 0.0 | 0.0 | 0 | 0 |
TS1005 | 0.0 | 0.0 | 0 | 0 |
TS1006 | 0.0 | 0.0 | 0 | 0 |
TS1007 | 0.0 | 0.0 | 0 | 0 |
TS1008 | 0.0 | 0.0 | 0 | 0 |
TS1009 | 0.0 | 0.0 | 0 | 0 |
TS1010 | 0.0 | 0.0 | 0 | 0 |
TS1011 | 0.0 | 0.0 | 0 | 0 |
TS1012 | 0.0 | 0.0 | 0 | 0 |
TS1013 | 0.0 | 0.0 | 0 | 0 |
TS1014 | 0.0 | 0.0 | 0 | 0 |
TS1015 | 0.0 | 0.0 | 0 | 0 |
TS1016 | 0.0 | 0.0 | 0 | 0 |
TS1017 | 0.0 | 0.0 | 0 | 0 |
TS1018 | 0.0 | 0.0 | 0 | 0 |
TS1019 | 0.0 | 0.0 | 0 | 0 |
TS1020 | 0.0 | 0.0 | 0 | 0 |
TS1021 | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_F2F | 0.0 | 0.0 | 0 | 0 |
AUTO_TS_P2P | 0.0 | 87.0 | 166 | 166 |
AUTO_TS_P2F | 0.0 | 24.0 | 27 | 27 |
AUTO_TS_F2P | 0.0 | 22.0 | 15 | 15 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
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Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
NMI to FREEZER_ROM | 0.000 | 87.000 | -87.000 |
NMI to OS_ROM | 0.000 | 87.000 | -87.000 |
NMI to RAM_RA0 | 0.000 | 87.000 | -87.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
A0 to XLXN_368.CLKF | 0.000 | 24.000 | -24.000 |
A1 to XLXN_368.CLKF | 0.000 | 24.000 | -24.000 |
A10 to XLXN_368.CLKF | 0.000 | 24.000 | -24.000 |
Path | Requirement (ns) | Delay (ns) | Slack (ns) |
---|---|---|---|
XLXN_267.Q to FREEZER_ROM | 0.000 | 22.000 | -22.000 |
XLXN_267.Q to OS_ROM | 0.000 | 22.000 | -22.000 |
XLXN_282.Q to FREEZER_ROM | 0.000 | 22.000 | -22.000 |
Clock | fEXT (MHz) | Reason |
---|---|---|
XLXN_349.Q | 71.429 | Limited by Clock Pulse Width for XLXN_349.Q |
XLXN_267.Q | 71.429 | Limited by Clock Pulse Width for XLXN_267.Q |
A0 | 71.429 | Limited by Clock Pulse Width for A0 |
A10 | 71.429 | Limited by Clock Pulse Width for A10 |
A8 | 71.429 | Limited by Clock Pulse Width for A8 |
A9 | 71.429 | Limited by Clock Pulse Width for A9 |
A3 | 71.429 | Limited by Clock Pulse Width for A3 |
A5 | 71.429 | Limited by Clock Pulse Width for A5 |
A7 | 71.429 | Limited by Clock Pulse Width for A7 |
A1 | 71.429 | Limited by Clock Pulse Width for A1 |
A4 | 71.429 | Limited by Clock Pulse Width for A4 |
A6 | 71.429 | Limited by Clock Pulse Width for A6 |
NMI | 100.000 | Limited by Clock Pulse Width for NMI |
A11 | 71.429 | Limited by Clock Pulse Width for A11 |
A13 | 71.429 | Limited by Clock Pulse Width for A13 |
A12 | 71.429 | Limited by Clock Pulse Width for A12 |
XLXN_368.Q | 71.429 | Limited by Clock Pulse Width for XLXN_368.Q |
A15 | 71.429 | Limited by Clock Pulse Width for A15 |
RW | 71.429 | Limited by Clock Pulse Width for RW |
D7xx | 71.429 | Limited by Clock Pulse Width for D7xx |
PHI_1 | 71.429 | Limited by Clock Pulse Width for PHI_1 |
A14 | 71.429 | Limited by Clock Pulse Width for A14 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
FREEZER | 8.000 | 0.000 |
Source Pad | Setup to clk (edge) | Hold to clk (edge) |
---|---|---|
HALT | 8.000 | 0.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 87.000 |
OS_ROM | 87.000 |
RAM_RA0 | 87.000 |
RAM_RA5 | 87.000 |
RAM_RA7 | 87.000 |
CASINH_FRED_4 | 56.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 46.000 |
OS_ROM | 46.000 |
RAM_RA0 | 46.000 |
RAM_RA5 | 46.000 |
RAM_RA7 | 46.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 46.000 |
OS_ROM | 46.000 |
RAM_RA0 | 46.000 |
RAM_RA5 | 46.000 |
RAM_RA7 | 46.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 87.000 |
OS_ROM | 87.000 |
RAM_RA0 | 87.000 |
RAM_RA5 | 87.000 |
RAM_RA7 | 87.000 |
CASINH_FRED_4 | 56.000 |
Destination Pad | Clock (edge) to Pad |
---|---|
FREEZER_ROM | 84.000 |
OS_ROM | 84.000 |
RAM_RA0 | 84.000 |
RAM_RA5 | 84.000 |
RAM_RA7 | 84.000 |
CASINH_FRED_4 | 53.000 |
Source Pad | Destination Pad | Delay |
---|---|---|
A0 | FREEZER_ROM | 15.000 |
A0 | OS_ROM | 15.000 |
A1 | FREEZER_ROM | 15.000 |
A1 | OS_ROM | 15.000 |
A10 | FREEZER_ROM | 15.000 |
A10 | OS_ROM | 15.000 |
A11 | FREEZER_ROM | 15.000 |
A11 | OS_ROM | 15.000 |
A11 | RAM_RA0 | 15.000 |
A11 | RAM_RA5 | 15.000 |
A11 | RAM_RA7 | 15.000 |
A12 | FREEZER_ROM | 15.000 |
A12 | OS_ROM | 15.000 |
A12 | RAM_RA0 | 15.000 |
A12 | RAM_RA5 | 15.000 |
A12 | RAM_RA7 | 15.000 |
A13 | FREEZER_ROM | 15.000 |
A13 | OS_ROM | 15.000 |
A13 | RAM_RA0 | 15.000 |
A13 | RAM_RA5 | 15.000 |
A13 | RAM_RA7 | 15.000 |
A14 | FREEZER_ROM | 15.000 |
A14 | OS_ROM | 15.000 |
A14 | RAM_RA0 | 15.000 |
A14 | RAM_RA5 | 15.000 |
A14 | RAM_RA7 | 15.000 |
A15 | FREEZER_ROM | 15.000 |
A15 | OS_ROM | 15.000 |
A15 | RAM_RA0 | 15.000 |
A15 | RAM_RA5 | 15.000 |
A15 | RAM_RA7 | 15.000 |
A3 | FREEZER_ROM | 15.000 |
A3 | OS_ROM | 15.000 |
A4 | FREEZER_ROM | 15.000 |
A4 | OS_ROM | 15.000 |
A5 | FREEZER_ROM | 15.000 |
A5 | OS_ROM | 15.000 |
A6 | FREEZER_ROM | 15.000 |
A6 | OS_ROM | 15.000 |
A7 | FREEZER_ROM | 15.000 |
A7 | OS_ROM | 15.000 |
A8 | FREEZER_ROM | 15.000 |
A8 | OS_ROM | 15.000 |
A9 | FREEZER_ROM | 15.000 |
A9 | OS_ROM | 15.000 |
CASINH_MMU_16 | CASINH_FRED_4 | 15.000 |
FRED25 | RAM_RA7 | 15.000 |
FRED27 | RAM_RA5 | 15.000 |
FRED32 | RAM_RA0 | 15.000 |
MMU_17 | CASINH_FRED_4 | 15.000 |
PHI_2 | RAM_RA0 | 15.000 |
PHI_2 | RAM_RA5 | 15.000 |
PHI_2 | RAM_RA7 | 15.000 |
RW | CASINH_FRED_4 | 15.000 |