Timing Report

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Design Name CPLDfreezer
Device, Speed (SpeedFile Version) XC9536, -15 (3.0)
Date Created Mon Dec 26 18:15:21 2011
Created By Timing Report Generator: version M.81d
Copyright Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.

Summary

Notes and Warnings
Note: This design contains no timing constraints.
Note: A default set of constraints using a delay of 0.000ns will be used for analysis.
Possible asynchronous logic: Clock pin 'XLXN_368.CLKF' has multiple original clock nets 'XLXN_349.Q' 'XLXN_267.Q' 'A0' 'A10' 'A8' 'A9' 'A3' 'A5' 'A7' 'A1' 'A4' 'A6' 'A11' 'A13' 'A12' 'XLXN_368.Q' 'A15' 'A14'.
Possible asynchronous logic: Clock pin 'XLXN_282.CLKF' has multiple original clock nets 'A11' 'A13' 'A12' 'XLXN_368.Q' 'A15' 'RW' 'D7xx' 'PHI_1' 'A14'.

Performance Summary
Min. Clock Period 14.000 ns.
Max. Clock Frequency (fSYSTEM) 71.429 MHz.
Limited by Clock Pulse Width for XLXN_349.Q
Pad to Pad Delay (tPD) 15.000 ns.
Setup to Clock at the Pad (tSU) 8.000 ns.
Clock Pad to Output Pad Delay (tCO) 87.000 ns.

Timing Constraints

Constraint Name Requirement (ns) Delay (ns) Paths Paths Failing
TS1000 0.0 0.0 0 0
TS1001 0.0 0.0 0 0
TS1002 0.0 0.0 0 0
TS1003 0.0 0.0 0 0
TS1004 0.0 0.0 0 0
TS1005 0.0 0.0 0 0
TS1006 0.0 0.0 0 0
TS1007 0.0 0.0 0 0
TS1008 0.0 0.0 0 0
TS1009 0.0 0.0 0 0
TS1010 0.0 0.0 0 0
TS1011 0.0 0.0 0 0
TS1012 0.0 0.0 0 0
TS1013 0.0 0.0 0 0
TS1014 0.0 0.0 0 0
TS1015 0.0 0.0 0 0
TS1016 0.0 0.0 0 0
TS1017 0.0 0.0 0 0
TS1018 0.0 0.0 0 0
TS1019 0.0 0.0 0 0
TS1020 0.0 0.0 0 0
TS1021 0.0 0.0 0 0
AUTO_TS_F2F 0.0 0.0 0 0
AUTO_TS_P2P 0.0 87.0 166 166
AUTO_TS_P2F 0.0 24.0 27 27
AUTO_TS_F2P 0.0 22.0 15 15


Constraint: TS1000

Description: PERIOD:PERIOD_XLXN_349.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1001

Description: PERIOD:PERIOD_XLXN_267.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1002

Description: PERIOD:PERIOD_A0:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1003

Description: PERIOD:PERIOD_A10:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1004

Description: PERIOD:PERIOD_A8:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1005

Description: PERIOD:PERIOD_A9:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1006

Description: PERIOD:PERIOD_A3:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1007

Description: PERIOD:PERIOD_A5:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1008

Description: PERIOD:PERIOD_A7:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1009

Description: PERIOD:PERIOD_A1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1010

Description: PERIOD:PERIOD_A4:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1011

Description: PERIOD:PERIOD_A6:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1012

Description: PERIOD:PERIOD_NMI:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1013

Description: PERIOD:PERIOD_A11:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1014

Description: PERIOD:PERIOD_A13:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1015

Description: PERIOD:PERIOD_A12:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1016

Description: PERIOD:PERIOD_XLXN_368.Q:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1017

Description: PERIOD:PERIOD_A15:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1018

Description: PERIOD:PERIOD_RW:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1019

Description: PERIOD:PERIOD_D7xx:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1020

Description: PERIOD:PERIOD_PHI_1:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: TS1021

Description: PERIOD:PERIOD_A14:0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_F2F

Description: MAXDELAY:FROM:FFS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)


Constraint: AUTO_TS_P2P

Description: MAXDELAY:FROM:PADS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
NMI to FREEZER_ROM 0.000 87.000 -87.000
NMI to OS_ROM 0.000 87.000 -87.000
NMI to RAM_RA0 0.000 87.000 -87.000


Constraint: AUTO_TS_P2F

Description: MAXDELAY:FROM:PADS(*):TO:FFS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
A0 to XLXN_368.CLKF 0.000 24.000 -24.000
A1 to XLXN_368.CLKF 0.000 24.000 -24.000
A10 to XLXN_368.CLKF 0.000 24.000 -24.000


Constraint: AUTO_TS_F2P

Description: MAXDELAY:FROM:FFS(*):TO:PADS(*):0.000 nS
Path Requirement (ns) Delay (ns) Slack (ns)
XLXN_267.Q to FREEZER_ROM 0.000 22.000 -22.000
XLXN_267.Q to OS_ROM 0.000 22.000 -22.000
XLXN_282.Q to FREEZER_ROM 0.000 22.000 -22.000



Number of constraints not met: 3

Data Sheet Report

Maximum External Clock Speeds

Clock fEXT (MHz) Reason
XLXN_349.Q 71.429 Limited by Clock Pulse Width for XLXN_349.Q
XLXN_267.Q 71.429 Limited by Clock Pulse Width for XLXN_267.Q
A0 71.429 Limited by Clock Pulse Width for A0
A10 71.429 Limited by Clock Pulse Width for A10
A8 71.429 Limited by Clock Pulse Width for A8
A9 71.429 Limited by Clock Pulse Width for A9
A3 71.429 Limited by Clock Pulse Width for A3
A5 71.429 Limited by Clock Pulse Width for A5
A7 71.429 Limited by Clock Pulse Width for A7
A1 71.429 Limited by Clock Pulse Width for A1
A4 71.429 Limited by Clock Pulse Width for A4
A6 71.429 Limited by Clock Pulse Width for A6
NMI 100.000 Limited by Clock Pulse Width for NMI
A11 71.429 Limited by Clock Pulse Width for A11
A13 71.429 Limited by Clock Pulse Width for A13
A12 71.429 Limited by Clock Pulse Width for A12
XLXN_368.Q 71.429 Limited by Clock Pulse Width for XLXN_368.Q
A15 71.429 Limited by Clock Pulse Width for A15
RW 71.429 Limited by Clock Pulse Width for RW
D7xx 71.429 Limited by Clock Pulse Width for D7xx
PHI_1 71.429 Limited by Clock Pulse Width for PHI_1
A14 71.429 Limited by Clock Pulse Width for A14

Setup/Hold Times for Clocks

Setup/Hold Times for Clock NMI
Source Pad Setup to clk (edge) Hold to clk (edge)
FREEZER 8.000 0.000

Setup/Hold Times for Clock PHI_1
Source Pad Setup to clk (edge) Hold to clk (edge)
HALT 8.000 0.000


Clock to Pad Timing

Clock A0 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A10 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A8 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A9 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A3 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A5 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A7 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A1 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A4 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A6 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock NMI to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 87.000
OS_ROM 87.000
RAM_RA0 87.000
RAM_RA5 87.000
RAM_RA7 87.000
CASINH_FRED_4 56.000

Clock A11 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A13 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A12 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock A15 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000

Clock RW to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 46.000
OS_ROM 46.000
RAM_RA0 46.000
RAM_RA5 46.000
RAM_RA7 46.000

Clock D7xx to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 46.000
OS_ROM 46.000
RAM_RA0 46.000
RAM_RA5 46.000
RAM_RA7 46.000

Clock PHI_1 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 87.000
OS_ROM 87.000
RAM_RA0 87.000
RAM_RA5 87.000
RAM_RA7 87.000
CASINH_FRED_4 56.000

Clock A14 to Pad
Destination Pad Clock (edge) to Pad
FREEZER_ROM 84.000
OS_ROM 84.000
RAM_RA0 84.000
RAM_RA5 84.000
RAM_RA7 84.000
CASINH_FRED_4 53.000


Clock to Setup Times for Clocks


Pad to Pad List

Source Pad Destination Pad Delay
A0 FREEZER_ROM 15.000
A0 OS_ROM 15.000
A1 FREEZER_ROM 15.000
A1 OS_ROM 15.000
A10 FREEZER_ROM 15.000
A10 OS_ROM 15.000
A11 FREEZER_ROM 15.000
A11 OS_ROM 15.000
A11 RAM_RA0 15.000
A11 RAM_RA5 15.000
A11 RAM_RA7 15.000
A12 FREEZER_ROM 15.000
A12 OS_ROM 15.000
A12 RAM_RA0 15.000
A12 RAM_RA5 15.000
A12 RAM_RA7 15.000
A13 FREEZER_ROM 15.000
A13 OS_ROM 15.000
A13 RAM_RA0 15.000
A13 RAM_RA5 15.000
A13 RAM_RA7 15.000
A14 FREEZER_ROM 15.000
A14 OS_ROM 15.000
A14 RAM_RA0 15.000
A14 RAM_RA5 15.000
A14 RAM_RA7 15.000
A15 FREEZER_ROM 15.000
A15 OS_ROM 15.000
A15 RAM_RA0 15.000
A15 RAM_RA5 15.000
A15 RAM_RA7 15.000
A3 FREEZER_ROM 15.000
A3 OS_ROM 15.000
A4 FREEZER_ROM 15.000
A4 OS_ROM 15.000
A5 FREEZER_ROM 15.000
A5 OS_ROM 15.000
A6 FREEZER_ROM 15.000
A6 OS_ROM 15.000
A7 FREEZER_ROM 15.000
A7 OS_ROM 15.000
A8 FREEZER_ROM 15.000
A8 OS_ROM 15.000
A9 FREEZER_ROM 15.000
A9 OS_ROM 15.000
CASINH_MMU_16 CASINH_FRED_4 15.000
FRED25 RAM_RA7 15.000
FRED27 RAM_RA5 15.000
FRED32 RAM_RA0 15.000
MMU_17 CASINH_FRED_4 15.000
PHI_2 RAM_RA0 15.000
PHI_2 RAM_RA5 15.000
PHI_2 RAM_RA7 15.000
RW CASINH_FRED_4 15.000



Number of paths analyzed: 208
Number of Timing errors: 208
Analysis Completed: Mon Dec 26 18:15:21 2011