IS-Plate: (Info by phaeron) Upgrade: I.S. Plate 1050 Manufacturer: Robert Perry, Innovative Software Year: 1986 Features: fully Happy 1050 compatible, board (fits 6507 socket) with 6502 and 16KiB RAM buffer. IS Doubler/US Doubler, Archiver/Chip, standard 1050 emulation, 16-drive support. Software included; IS Doubler/US Doubler high-speed disk copiers (standard and 130XE versions), file loader, custom disk format (incl bad sectors), track tracer Late units: Software instead built-in on ROM Early units: ISP Gremlin Grabber (sold separately) Most units included Gremlin Grabber II or Gremlin Grabber III Commands: 20, 21, 22, 3F, 41, 44, 4B, 4C, 4D, 4E, 4F, 50, 51, 52, 53, 57, 60, 62, 68, 69 Now, about the I.S. Plate.... First of all, this thing deserves an award for the most confused naming. Just in the first two pages of the device's own manual it is called the I.S. 1050 Plate, the 1050 ISP Disk Drive, the 1050 ISP, the ISP Plate, the ISP PLATE, and the 1050 ISP PLATE. I gave up trying to determine the true official name and used I.S. Plate. Regarding the emulation, the I.S. Plate's memory map is pretty simple: $0000-7FFF: 1050 $0000-0FFF mirrored 8x $8000-9FFF: 8K RAM $C000-DFFF: 8K RAM $E000-FFFF: 4K ROM mirrored I have no idea why the second 8K of RAM was put at $C000 instead of $A000, since it would have only needed moving a trace over by one pin on the decoder. Accurate sector timing is forced on for I.S. Plate emulated drives. The reason is a bug in the firmware that took me a bit to work out. The firmware blindly scans for sectors during density detection for a quarter of a second and puts the sector numbers into an array without any checks. If it sees more than about 100 sectors within 0.25s the firmware overwrites its stack and crashes, due to the 1050 having pages 0 and 1 mirrored. Fortunately the firmware also has track buffering, so the read speed is generally still good. Write buffering is also supported but not enabled by default; disk copies will go pretty slowly if this is not manually enabled. The I.S. Plate, like the Happy, replaces the 6507 on the 1050 with a 6502 to increase the address space from 8K to 64K. 8K of RAM on the I.S. Plate is in the same place as Happy's 6K/8K, but the ROM is different as the Happy switches between two banks of 4K while the ISP just has 8K of flat ROM. This means that you can't just run a Happy ROM on the ISP, it has to be one written for or converted for the ISP. Happy code might work in this environment, but it would not be too hard to write code in a way that would break on a Happy emulator on the ISP. Incidentally, Altirra currently only loads and double-maps the first 4K of the ROM; I'll expand this to optional support for 8K later. The ISP and Happy configuration software have eerily similar interfaces. I don't know if this was just aggressive mimicry or not; checking the software disks in a hex editor didn't reveal obvious copying. The ISP diagnostic also runs much faster, to the point that I doubt whether it is even testing all of the RAM. Gremlin Grabber works for me as well, but try with test-21 as the crash bug could also have caused the ISP emulation to intermittently malfunction. Also on the IS Plate -- if you boot the ISP Lightspeed software and load IS/US Doubler emulation onto the drive, the drive won't respond anymore if the computer is NTSC, due to a bug introduced into the transmit routine by Innovated Software when converting the US Doubler firmware to the I.S. Plate. Spot the bug: C2EA: 6E 35 01 LC2EA ROR $0135 C2ED: 90 07 BCC LC2F6 C2EF: A9 01 LDA #$01 C2F1: 0D 82 02 ORA $0282 C2F4: D0 06 BNE LC2FC C2F6: A9 FE LC2F6 LDA #$FE C2F8: 2D 82 02 AND $0282 C2FB: EA NOP C2FC: A0 04 LC2FC LDY #$04 C2FE: 88 LC2FE DEY C2FF: D0 FD BNE LC2FE C301: EA NOP C302: 8D 82 02 STA $0282 C305: CE 34 01 DEC $0134 C308: D0 E0 BNE LC2EA The 1050 has page 0 and page 1 mirrored onto the same 256 bytes of RAM -- the firmware has to map its variables around the stack. Fortunately, the 6502's weakness at stack parameter passing means that very little stack is needed... and as a few daring programmers have shown, you can get by with no stack. The NOP isn't the problem, as that's needed to balance the branch timing between 0 and 1 bits. This is the problem: C2FF: D0 FD BNE LC2FE Although it doesn't look like one, that is a page crossing branch. The people who relocated the US Doubler code to the I.S. Plate failed to notice that they had moved the transmit routine to a place where both of its critical loops overlapped a page boundary. This added four cycles per bit to the transmit timing, which changes it from fairly well tuned to way off. Ideal timing is 53 cycles/bit, this does 57... barely viable for PAL and beyond tolerance for NTSC. As for the computer-only reset, it is possible for a drive to get stuck if its in the middle of a command, which could lead to problems on the next boot. Drives often don't have a timeout or recovery mechanism; once they need 128 bytes they'll patiently wait for 128 bytes no matter what, even if the computer long ago gave up on the original command and is trying to get a new command through. But you'd know that pretty quickly.