Logic

Signal Name Total Pterms Total Inputs Function Block Macrocell Power Mode Slew Rate Pin Number Pin Type Pin Use Reg Init State
N177/N177_D2 1 4 FB1 MC1 LOW     (b) (b)  
N76/N76_D2 2 7 FB1 MC2 LOW   11 I/O I  
rom_ce 9 13 FB1 MC3 LOW SLOW 12 I/O O  
$OpTx$FX_DC$578 2 2 FB1 MC4 LOW     (b) (b)  
data<0> 8 20 FB1 MC6 LOW SLOW 14 I/O I/O  
N28/N28_D2 3 9 FB1 MC7 LOW     (b) (b)  
data<2> 7 17 FB1 MC8 LOW SLOW 15 I/O I/O  
data<1> 6 16 FB1 MC9 LOW SLOW 16 I/O I/O  
check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 6 8 FB1 MC10 LOW     (b) (b)  
data<6> 2 10 FB1 MC11 LOW SLOW 17 I/O I/O  
data<5> 4 13 FB1 MC12 LOW SLOW 18 I/O I/O  
$OpTx$FX_DC$652 10 14 FB1 MC13 LOW     (b) (b)  
data<4> 5 14 FB1 MC14 LOW SLOW 19 I/O I/O  
data<3> 7 17 FB1 MC15 LOW SLOW 20 I/O I/O  
$OpTx$FX_DC$594 2 5 FB1 MC16 LOW     (b) (b)  
data<7> 14 21 FB1 MC17 LOW SLOW 22 I/O/GCK1 I/O  
data_0_cmp_eq0005/data_0_cmp_eq0005_D2 1 16 FB2 MC1 LOW     (b) (b)  
reset 1 1 FB2 MC2 LOW   99 I/O/GSR I RESET
data_0_cmp_eq0004/data_0_cmp_eq0004_D2 1 16 FB2 MC3 LOW     (b) (b)  
ram_rom_adr<14> 11 13 FB2 MC5 LOW SLOW 1 I/O/GTS3 O  
ram_rom_adr<13> 18 18 FB2 MC6 LOW SLOW 2 I/O/GTS4 O  
turbo_speed_out 3 8 FB2 MC8 LOW SLOW 3 I/O/GTS1 O  
data_0_cmp_eq0002/data_0_cmp_eq0002_D2 1 16 FB2 MC9 LOW   4 I/O/GTS2 I  
data_0_cmp_eq0001/data_0_cmp_eq0001_D2 1 16 FB2 MC10 LOW     (b) (b)  
data_0_cmp_eq0000/data_0_cmp_eq0000_D2 1 16 FB2 MC11 LOW   6 I/O I  
ram_rom_adr<9> 1 2 FB2 MC12 LOW SLOW 7 I/O O  
$OpTx$FX_DC$670 1 19 FB2 MC13 LOW     (b) (b)  
$OpTx$FX_DC$583 1 16 FB2 MC14 LOW   8 I/O I  
ram_bank_1 3 14 FB2 MC15 LOW   9 I/O I RESET
happy_a12 3 19 FB2 MC16 LOW     (b) (b) RESET
$OpTx$INV$575 4 17 FB2 MC17 LOW   10 I/O I  
N27/N27_D2 8 12 FB2 MC18 LOW     (b) (b)  
track_hi<5> 5 15 FB3 MC1 LOW     (b) (b) SET
i2c_clk_and0000/i2c_clk_and0000_D2 1 14 FB3 MC2 LOW   23 I/O/GCK2 I  
data_0_cmp_eq0006/data_0_cmp_eq0006_D2 1 16 FB3 MC3 LOW     (b) (b)  
$OpTx$FX_DC$626 1 14 FB3 MC4 LOW     (b) (b)  
io_1050 7 10 FB3 MC5 LOW SLOW 24 I/O O  
ram_bank_5 2 12 FB3 MC6 LOW   25 I/O I RESET
track_hi<1> 3 11 FB3 MC7 LOW     (b) (b) SET
N3/N3_D2 3 10 FB3 MC8 LOW   27 I/O/GCK3 GCK/I  
ram_rom_adr<11> 9 11 FB3 MC9 LOW SLOW 28 I/O O  
N2/N2_D2 3 10 FB3 MC10 LOW     (b) (b)  
ram_rom_adr<8> 8 10 FB3 MC11 LOW SLOW 29 I/O O  
$OpTx$FX_DC$627 3 10 FB3 MC12 LOW   30 I/O I  
track_hi<4> 4 14 FB3 MC13 LOW     (b) (b) SET
density<1> 4 15 FB3 MC14 LOW   32 I/O I SET
ram_rom_adr<12> 23 17 FB3 MC17 LOW SLOW 34 I/O O  
track_lo<0> 7 17 FB4 MC1 LOW     (b) (b) SET
track_lo_out<3> 1 1 FB4 MC2 LOW SLOW 87 I/O O  
ram_bank_4 3 14 FB4 MC3 LOW     (b) (b) RESET
ram_bank_3 3 14 FB4 MC4 LOW     (b) (b) RESET
track_lo_out<2> 1 1 FB4 MC5 LOW SLOW 89 I/O O  
track_lo_out<1> 1 1 FB4 MC6 LOW SLOW 90 I/O O  
ram_bank_2 3 14 FB4 MC7 LOW     (b) (b) RESET
track_lo_out<0> 1 1 FB4 MC8 LOW SLOW 91 I/O O  
ram_bank_0 3 14 FB4 MC9 LOW   92 I/O I RESET
track_lo<4> 6 18 FB4 MC10 LOW     (b) (b) SET
track_lo<1> 7 17 FB4 MC11 LOW   93 I/O I SET
ram_rom_adr<18> 7 15 FB4 MC12 LOW SLOW 94 I/O O  
ram_rom_adr<17> 6 15 FB4 MC14 LOW SLOW 95 I/O O  
ram_rom_adr<16> 6 15 FB4 MC15 LOW SLOW 96 I/O O  
ram_rom_adr<15> 18 19 FB4 MC17 LOW SLOW 97 I/O O  
turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 2 8 FB5 MC1 LOW     (b) (b)  
floppy_mode<3> 2 6 FB5 MC2 LOW   35 I/O I RESET
floppy_mode<2> 2 6 FB5 MC3 LOW     (b) (b) RESET
$OpTx$INV$574 2 9 FB5 MC4 LOW     (b) (b)  
$OpTx$FX_DC$598 2 8 FB5 MC5 LOW   36 I/O I  
ms_write_enable 3 8 FB5 MC6 LOW   37 I/O I SET
ms_speed_select 3 8 FB5 MC7 LOW     (b) (b) SET
i2c_data 3 8 FB5 MC8 LOW   39 I/O I SET
i2c_clk 3 8 FB5 MC9 LOW   40 I/O I SET
floppy_mode<1> 3 7 FB5 MC10 LOW     (b) (b) SET
ram_rom_adr<10> 3 8 FB5 MC11 LOW SLOW 41 I/O O  
ram_ce 21 16 FB5 MC12 LOW SLOW 42 I/O O  
d7_ram_rom 2 4 FB5 MC15 LOW SLOW 46 I/O I/O  
floppy_mode<0> 3 7 FB5 MC16 LOW     (b) (b) SET
ram_rom_oe 1 2 FB5 MC17 LOW SLOW 49 I/O O  
data_7_mux0000/data_7_mux0000_TRST 4 12 FB5 MC18 LOW     (b) (b)  
reset_sync 1 1 FB6 MC1 LOW     (b) (b) RESET
track_hi_out<5> 1 1 FB6 MC2 LOW SLOW 74 I/O O  
N120/N120_D2 1 4 FB6 MC3 LOW     (b) (b)  
rom_source_is_ram 2 4 FB6 MC4 LOW     (b) (b) RESET
track_hi_out<4> 1 1 FB6 MC5 LOW SLOW 76 I/O O  
track_hi_out<3> 1 1 FB6 MC6 LOW SLOW 77 I/O O  
rom_base_bank_6 2 4 FB6 MC7 LOW     (b) (b) SET
track_hi_out<2> 1 1 FB6 MC8 LOW SLOW 78 I/O O  
track_hi_out<1> 1 1 FB6 MC9 LOW SLOW 79 I/O O  
rom_base_bank_5 2 4 FB6 MC10 LOW     (b) (b) SET
rom_base_bank_4 2 4 FB6 MC11 LOW   80 I/O I SET
track_hi_out<0> 1 1 FB6 MC12 LOW SLOW 81 I/O O  
rom_base_bank_3 2 4 FB6 MC13 LOW     (b) (b) SET
track_lo_out<6> 1 1 FB6 MC14 LOW SLOW 82 I/O O  
track_lo_out<5> 1 1 FB6 MC15 LOW SLOW 85 I/O O  
rom_base_bank_2 2 4 FB6 MC16 LOW     (b) (b) RESET
track_lo_out<4> 1 1 FB6 MC17 LOW SLOW 86 I/O O  
rom_base_bank_1 2 4 FB6 MC18 LOW     (b) (b) RESET
turbo_rom_adr<12> 2 4 FB7 MC1 LOW     (b) (b) SET
ram_rom_we 1 2 FB7 MC2 LOW SLOW 50 I/O O  
turbo_rom_adr<11> 2 5 FB7 MC3 LOW     (b) (b) SET
rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 2 5 FB7 MC4 LOW     (b) (b)  
fdc_write_out 3 7 FB7 MC5 LOW SLOW 52 I/O O  
rom_base_bank_0 2 4 FB7 MC6 LOW   53 I/O I RESET
rom_bank_c000_enable<0> 2 4 FB7 MC7 LOW     (b) (b) RESET
rom_bank_c000_5 2 4 FB7 MC8 LOW   54 I/O I RESET
riot_ready_inout 2 5 FB7 MC9 LOW SLOW 55 I/O I/O  
rom_bank_c000_4 2 4 FB7 MC10 LOW     (b) (b) RESET
cfg_led 2 4 FB7 MC11 LOW SLOW 56 I/O O RESET
rom_bank_c000_3 2 4 FB7 MC12 LOW   58 I/O I RESET
rom_bank_c000_2 2 4 FB7 MC13 LOW     (b) (b) RESET
i2c_clk_pin 1 1 FB7 MC14 LOW SLOW 59 I/O O  
i2c_data_pin 1 1 FB7 MC15 LOW SLOW 60 I/O I/O  
rom_bank_c000_1 2 4 FB7 MC16 LOW     (b) (b) RESET
rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2 6 FB7 MC17 LOW   61 I/O I  
rom_bank_c000_0 2 4 FB7 MC18 LOW     (b) (b) RESET
track_hi<6> 4 15 FB8 MC1 LOW     (b) (b) SET
track_hi<3> 4 16 FB8 MC2 LOW   63 I/O I SET
track_hi<2> 4 16 FB8 MC3 LOW     (b) (b) SET
track_hi<0> 4 16 FB8 MC4 LOW     (b) (b) SET
centronics_data 4 15 FB8 MC5 LOW SLOW 64 I/O O SET
centronics_strobe 8 14 FB8 MC6 LOW SLOW 65 I/O O SET
density<2> 4 15 FB8 MC7 LOW     (b) (b) SET
centronics_clk 4 15 FB8 MC8 LOW SLOW 66 I/O O SET
summer 2 11 FB8 MC9 LOW SLOW 67 I/O O RESET
density<0> 5 16 FB8 MC10 LOW     (b) (b) SET
density_out<2> 1 1 FB8 MC11 LOW SLOW 68 I/O O  
density_out<1> 1 1 FB8 MC12 LOW SLOW 70 I/O O  
track_lo<6> 6 18 FB8 MC13 LOW     (b) (b) SET
density_out<0> 1 1 FB8 MC14 LOW SLOW 71 I/O O  
track_hi_out<6> 1 1 FB8 MC15 LOW SLOW 72 I/O O  
track_lo<2> 6 17 FB8 MC16 LOW     (b) (b) SET
track_lo<5> 7 18 FB8 MC17 LOW   73 I/O I SET
track_lo<3> 7 17 FB8 MC18 LOW     (b) (b) SET