cpldfit: version P.20131013 Xilinx Inc. Fitter Report Design Name: MegaSpeedy Date: 6-12-2017, 10:22PM Device Used: XC95144XL-10-TQ100 Fitting Status: Successful ************************* Mapped Resource Summary ************************** Macrocells Product Terms Function Block Registers Pins Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot 132/144 ( 92%) 488 /720 ( 68%) 340/432 ( 79%) 56 /144 ( 39%) 81 /81 (100%) ** Function Block Resources ** Function Mcells FB Inps Pterms IO Block Used/Tot Used/Tot Used/Tot Used/Tot FB1 16/18 53/54 88/90 11/11* FB2 16/18 41/54 59/90 10/10* FB3 15/18 45/54 77/90 10/10* FB4 15/18 47/54 73/90 10/10* FB5 16/18 41/54 59/90 10/10* FB6 18/18* 30/54 25/90 10/10* FB7 18/18* 39/54 34/90 10/10* FB8 18/18* 44/54 73/90 10/10* ----- ----- ----- ----- 132/144 340/432 488/720 81/81 * - Resource is exhausted ** Global Control Resources ** Signal 'phi2' mapped onto global clock net GCK3. Global output enable net(s) unused. Global set/reset net(s) unused. ** Pin Resources ** Signal Type Required Mapped | Pin Type Used Total ------------------------------------|------------------------------------ Input : 28 28 | I/O : 73 73 Output : 41 41 | GCK/IO : 3 3 Bidirectional : 11 11 | GTS/IO : 4 4 GCK : 1 1 | GSR/IO : 1 1 GTS : 0 0 | GSR : 0 0 | ---- ---- Total 81 81 ** Power Data ** There are 0 macrocells in high performance mode (MCHP). There are 132 macrocells in low power mode (MCLP). End of Mapped Resource Summary ************************** Errors and Warnings *************************** WARNING:Cpld - Unable to retrieve the path to the iSE Project Repository. Will use the default filename of 'MegaSpeedy.ise'. INFO:Cpld - Inferring BUFG constraint for signal 'data<7>' based upon the LOC constraint 'P22'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. INFO:Cpld - Inferring BUFG constraint for signal 'rw' based upon the LOC constraint 'P23'. It is recommended that you declare this BUFG explicitedly in your design. Note that for certain device families the output of a BUFG constraint can not drive a gated clock, and the BUFG constraint will be ignored. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'rw_IBUF' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. WARNING:Cpld:1239 - The global clock designation (BUFG) on signal 'd7_ram_rom_IOBUFE' is ignored. Most likely the signal is gated and therefore cannot be used as a global control signal. INFO:Cpld:994 - Exhaustive fitting is trying pterm limit: 23 and input limit: 21 ************************* Summary of Mapped Logic ************************ ** 52 Outputs ** Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State rom_ce 9 13 FB1_3 12 I/O O LOW SLOW data<0> 8 20 FB1_6 14 I/O I/O LOW SLOW data<2> 7 17 FB1_8 15 I/O I/O LOW SLOW data<1> 6 16 FB1_9 16 I/O I/O LOW SLOW data<6> 2 10 FB1_11 17 I/O I/O LOW SLOW data<5> 4 13 FB1_12 18 I/O I/O LOW SLOW data<4> 5 14 FB1_14 19 I/O I/O LOW SLOW data<3> 7 17 FB1_15 20 I/O I/O LOW SLOW data<7> 14 21 FB1_17 22 GCK/I/O I/O LOW SLOW ram_rom_adr<14> 11 13 FB2_5 1 GTS/I/O O LOW SLOW ram_rom_adr<13> 18 18 FB2_6 2 GTS/I/O O LOW SLOW turbo_speed_out 3 8 FB2_8 3 GTS/I/O O LOW SLOW ram_rom_adr<9> 1 2 FB2_12 7 I/O O LOW SLOW io_1050 7 10 FB3_5 24 I/O O LOW SLOW ram_rom_adr<11> 9 11 FB3_9 28 I/O O LOW SLOW ram_rom_adr<8> 8 10 FB3_11 29 I/O O LOW SLOW ram_rom_adr<12> 23 17 FB3_17 34 I/O O LOW SLOW track_lo_out<3> 1 1 FB4_2 87 I/O O LOW SLOW track_lo_out<2> 1 1 FB4_5 89 I/O O LOW SLOW track_lo_out<1> 1 1 FB4_6 90 I/O O LOW SLOW track_lo_out<0> 1 1 FB4_8 91 I/O O LOW SLOW ram_rom_adr<18> 7 15 FB4_12 94 I/O O LOW SLOW ram_rom_adr<17> 6 15 FB4_14 95 I/O O LOW SLOW ram_rom_adr<16> 6 15 FB4_15 96 I/O O LOW SLOW ram_rom_adr<15> 18 19 FB4_17 97 I/O O LOW SLOW ram_rom_adr<10> 3 8 FB5_11 41 I/O O LOW SLOW ram_ce 21 16 FB5_12 42 I/O O LOW SLOW d7_ram_rom 2 4 FB5_15 46 I/O I/O LOW SLOW ram_rom_oe 1 2 FB5_17 49 I/O O LOW SLOW track_hi_out<5> 1 1 FB6_2 74 I/O O LOW SLOW track_hi_out<4> 1 1 FB6_5 76 I/O O LOW SLOW track_hi_out<3> 1 1 FB6_6 77 I/O O LOW SLOW track_hi_out<2> 1 1 FB6_8 78 I/O O LOW SLOW track_hi_out<1> 1 1 FB6_9 79 I/O O LOW SLOW track_hi_out<0> 1 1 FB6_12 81 I/O O LOW SLOW track_lo_out<6> 1 1 FB6_14 82 I/O O LOW SLOW track_lo_out<5> 1 1 FB6_15 85 I/O O LOW SLOW track_lo_out<4> 1 1 FB6_17 86 I/O O LOW SLOW ram_rom_we 1 2 FB7_2 50 I/O O LOW SLOW fdc_write_out 3 7 FB7_5 52 I/O O LOW SLOW Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init Name Pts Inps No. Type Use Mode Rate State riot_ready_inout 2 5 FB7_9 55 I/O I/O LOW SLOW cfg_led 2 4 FB7_11 56 I/O O LOW SLOW RESET i2c_clk_pin 1 1 FB7_14 59 I/O O LOW SLOW i2c_data_pin 1 1 FB7_15 60 I/O I/O LOW SLOW centronics_data 4 15 FB8_5 64 I/O O LOW SLOW SET centronics_strobe 8 14 FB8_6 65 I/O O LOW SLOW SET centronics_clk 4 15 FB8_8 66 I/O O LOW SLOW SET summer 2 11 FB8_9 67 I/O O LOW SLOW RESET density_out<2> 1 1 FB8_11 68 I/O O LOW SLOW density_out<1> 1 1 FB8_12 70 I/O O LOW SLOW density_out<0> 1 1 FB8_14 71 I/O O LOW SLOW track_hi_out<6> 1 1 FB8_15 72 I/O O LOW SLOW ** 80 Buried Nodes ** Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State N177/N177_D2 1 4 FB1_1 LOW N76/N76_D2 2 7 FB1_2 LOW $OpTx$FX_DC$578 2 2 FB1_4 LOW N28/N28_D2 3 9 FB1_7 LOW check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 6 8 FB1_10 LOW $OpTx$FX_DC$652 10 14 FB1_13 LOW $OpTx$FX_DC$594 2 5 FB1_16 LOW data_0_cmp_eq0005/data_0_cmp_eq0005_D2 1 16 FB2_1 LOW reset 1 1 FB2_2 LOW RESET data_0_cmp_eq0004/data_0_cmp_eq0004_D2 1 16 FB2_3 LOW data_0_cmp_eq0002/data_0_cmp_eq0002_D2 1 16 FB2_9 LOW data_0_cmp_eq0001/data_0_cmp_eq0001_D2 1 16 FB2_10 LOW data_0_cmp_eq0000/data_0_cmp_eq0000_D2 1 16 FB2_11 LOW $OpTx$FX_DC$670 1 19 FB2_13 LOW $OpTx$FX_DC$583 1 16 FB2_14 LOW ram_bank_1 3 14 FB2_15 LOW RESET happy_a12 3 19 FB2_16 LOW RESET $OpTx$INV$575 4 17 FB2_17 LOW N27/N27_D2 8 12 FB2_18 LOW track_hi<5> 5 15 FB3_1 LOW SET i2c_clk_and0000/i2c_clk_and0000_D2 1 14 FB3_2 LOW data_0_cmp_eq0006/data_0_cmp_eq0006_D2 1 16 FB3_3 LOW $OpTx$FX_DC$626 1 14 FB3_4 LOW ram_bank_5 2 12 FB3_6 LOW RESET track_hi<1> 3 11 FB3_7 LOW SET N3/N3_D2 3 10 FB3_8 LOW N2/N2_D2 3 10 FB3_10 LOW $OpTx$FX_DC$627 3 10 FB3_12 LOW track_hi<4> 4 14 FB3_13 LOW SET density<1> 4 15 FB3_14 LOW SET track_lo<0> 7 17 FB4_1 LOW SET ram_bank_4 3 14 FB4_3 LOW RESET ram_bank_3 3 14 FB4_4 LOW RESET ram_bank_2 3 14 FB4_7 LOW RESET ram_bank_0 3 14 FB4_9 LOW RESET track_lo<4> 6 18 FB4_10 LOW SET track_lo<1> 7 17 FB4_11 LOW SET turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 2 8 FB5_1 LOW floppy_mode<3> 2 6 FB5_2 LOW RESET floppy_mode<2> 2 6 FB5_3 LOW RESET Signal Total Total Loc Pwr Reg Init Name Pts Inps Mode State $OpTx$INV$574 2 9 FB5_4 LOW $OpTx$FX_DC$598 2 8 FB5_5 LOW ms_write_enable 3 8 FB5_6 LOW SET ms_speed_select 3 8 FB5_7 LOW SET i2c_data 3 8 FB5_8 LOW SET i2c_clk 3 8 FB5_9 LOW SET floppy_mode<1> 3 7 FB5_10 LOW SET floppy_mode<0> 3 7 FB5_16 LOW SET data_7_mux0000/data_7_mux0000_TRST 4 12 FB5_18 LOW reset_sync 1 1 FB6_1 LOW RESET N120/N120_D2 1 4 FB6_3 LOW rom_source_is_ram 2 4 FB6_4 LOW RESET rom_base_bank_6 2 4 FB6_7 LOW SET rom_base_bank_5 2 4 FB6_10 LOW SET rom_base_bank_4 2 4 FB6_11 LOW SET rom_base_bank_3 2 4 FB6_13 LOW SET rom_base_bank_2 2 4 FB6_16 LOW RESET rom_base_bank_1 2 4 FB6_18 LOW RESET turbo_rom_adr<12> 2 4 FB7_1 LOW SET turbo_rom_adr<11> 2 5 FB7_3 LOW SET rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 2 5 FB7_4 LOW rom_base_bank_0 2 4 FB7_6 LOW RESET rom_bank_c000_enable<0> 2 4 FB7_7 LOW RESET rom_bank_c000_5 2 4 FB7_8 LOW RESET rom_bank_c000_4 2 4 FB7_10 LOW RESET rom_bank_c000_3 2 4 FB7_12 LOW RESET rom_bank_c000_2 2 4 FB7_13 LOW RESET rom_bank_c000_1 2 4 FB7_16 LOW RESET rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2 6 FB7_17 LOW rom_bank_c000_0 2 4 FB7_18 LOW RESET track_hi<6> 4 15 FB8_1 LOW SET track_hi<3> 4 16 FB8_2 LOW SET track_hi<2> 4 16 FB8_3 LOW SET track_hi<0> 4 16 FB8_4 LOW SET density<2> 4 15 FB8_7 LOW SET density<0> 5 16 FB8_10 LOW SET track_lo<6> 6 18 FB8_13 LOW SET track_lo<2> 6 17 FB8_16 LOW SET track_lo<5> 7 18 FB8_17 LOW SET track_lo<3> 7 17 FB8_18 LOW SET ** 29 Inputs ** Signal Loc Pin Pin Pin Name No. Type Use adr<1> FB1_2 11 I/O I adr<0> FB1_5 13 I/O I reset_in FB2_2 99 GSR/I/O I turbo_speed_in FB2_9 4 GTS/I/O I adr<5> FB2_11 6 I/O I adr<4> FB2_14 8 I/O I adr<3> FB2_15 9 I/O I adr<2> FB2_17 10 I/O I rw FB3_2 23 GCK/I/O I adr<6> FB3_6 25 I/O I phi2 FB3_8 27 GCK/I/O GCK/I adr<7> FB3_12 30 I/O I adr<8> FB3_14 32 I/O I adr<9> FB3_15 33 I/O I cfg_enc_a FB4_9 92 I/O I cfg_enc_b FB4_11 93 I/O I adr<10> FB5_2 35 I/O I adr<11> FB5_5 36 I/O I adr<13> FB5_6 37 I/O I adr<14> FB5_8 39 I/O I adr<15> FB5_9 40 I/O I adr<12> FB5_14 43 I/O I cfg_sw1 FB6_11 80 I/O I archiver_a11 FB7_6 53 I/O I fdc_write_in FB7_8 54 I/O I riot_ready_in FB7_12 58 I/O I cfg_sw2 FB7_17 61 I/O I centronics_busy FB8_2 63 I/O I cfg_enc_ok FB8_17 73 I/O I Legend: Pin No. - ~ - User Assigned ************************** Function Block Details ************************ Legend: Total Pt - Total product terms used by the macrocell signal Imp Pt - Product terms imported from other macrocells Exp Pt - Product terms exported to other macrocells in direction shown Unused Pt - Unused local product terms remaining in macrocell Loc - Location where logic was mapped in device Pin Type/Use - I - Input GCK - Global Clock O - Output GTS - Global Output Enable (b) - Buried macrocell GSR - Global Set/Reset X - Signal used as input to the macrocell logic. Pin No. - ~ - User Assigned *********************************** FB1 *********************************** Number of function block inputs used/remaining: 53/1 Number of signals used by logic mapping into function block: 53 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use N177/N177_D2 1 0 /\4 0 FB1_1 (b) (b) N76/N76_D2 2 0 \/1 2 FB1_2 11 I/O I rom_ce 9 4<- 0 0 FB1_3 12 I/O O $OpTx$FX_DC$578 2 0 /\3 0 FB1_4 (b) (b) (unused) 0 0 \/5 0 FB1_5 13 I/O I data<0> 8 5<- \/2 0 FB1_6 14 I/O I/O N28/N28_D2 3 2<- \/4 0 FB1_7 (b) (b) data<2> 7 4<- \/2 0 FB1_8 15 I/O I/O data<1> 6 2<- \/1 0 FB1_9 16 I/O I/O check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 6 1<- 0 0 FB1_10 (b) (b) data<6> 2 0 \/3 0 FB1_11 17 I/O I/O data<5> 4 3<- \/4 0 FB1_12 18 I/O I/O $OpTx$FX_DC$652 10 5<- 0 0 FB1_13 (b) (b) data<4> 5 1<- /\1 0 FB1_14 19 I/O I/O data<3> 7 3<- /\1 0 FB1_15 20 I/O I/O $OpTx$FX_DC$594 2 0 /\3 0 FB1_16 (b) (b) data<7> 14 9<- 0 0 FB1_17 22 GCK/I/O I/O (unused) 0 0 /\5 0 FB1_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$578 19: data_0_cmp_eq0000/data_0_cmp_eq0000_D2 37: rom_bank_c000_0 2: $OpTx$FX_DC$583 20: data_0_cmp_eq0001/data_0_cmp_eq0001_D2 38: rom_bank_c000_1 3: $OpTx$INV$575 21: data_0_cmp_eq0002/data_0_cmp_eq0002_D2 39: rom_bank_c000_2 4: N177/N177_D2 22: data_0_cmp_eq0004/data_0_cmp_eq0004_D2 40: rom_bank_c000_3 5: i2c_data_pin.PIN 23: data_0_cmp_eq0005/data_0_cmp_eq0005_D2 41: rom_bank_c000_4 6: d7_ram_rom.PIN 24: data_0_cmp_eq0006/data_0_cmp_eq0006_D2 42: rom_bank_c000_5 7: adr<11> 25: data_7_mux0000/data_7_mux0000_TRST 43: rom_bank_c000_enable<0> 8: adr<12> 26: fdc_write_in 44: rom_base_bank_0 9: adr<13> 27: floppy_mode<0> 45: rom_base_bank_1 10: adr<14> 28: floppy_mode<1> 46: rom_base_bank_2 11: adr<15> 29: floppy_mode<2> 47: rom_base_bank_3 12: archiver_a11 30: floppy_mode<3> 48: rom_base_bank_4 13: centronics_busy 31: i2c_clk_and0000/i2c_clk_and0000_D2 49: rom_base_bank_5 14: cfg_enc_a 32: ms_speed_select 50: rom_base_bank_6 15: cfg_enc_b 33: ms_write_enable 51: rom_source_is_ram 16: cfg_enc_ok 34: phi2 52: rw 17: cfg_sw1 35: ram_ce 53: turbo_speed_in 18: cfg_sw2 36: riot_ready_in Signal 1 2 3 4 5 6 FB Name 0----+----0----+----0----+----0----+----0----+----0----+----0 Inputs N177/N177_D2 .X...................XXX.................................... 4 N76/N76_D2 X.......XXX.................XX............X................. 7 rom_ce X.....XXXXX...............XXXX............X.......XX........ 13 $OpTx$FX_DC$578 ..........................XX................................ 2 data<0> XXX..........X....XXXXXX..X.XX.XXX..X......X.......XX....... 20 N28/N28_D2 .......XXXX...............XXXX.....................X........ 9 data<2> XXXX...........X..XXX.......XX...X.X..X...X..XX....X........ 17 data<1> XXXX.......X..X...XXX......XXX...X...X......X......X........ 16 check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 .......XXXX...............XXXX.............................. 8 data<6> X.X...............XXX.......XX...X...............X.X........ 10 data<5> X.X...............XXX.......XX...X.......XX.....XX.X........ 13 $OpTx$FX_DC$652 X.....XXXXX...............XXXX....X.......X.......XX........ 14 data<4> X.X..............XXXX.......XX...X......X.X....XX..X........ 14 data<3> XXXX............X.XXX....X..XX...X.....X..X...XX...X........ 17 $OpTx$FX_DC$594 ........X.................XXXX.............................. 5 data<7> XXX.XXXX....X.....XXXX..X.XXXXX...........X.......XX........ 21 0----+----1----+----2----+----3----+----4----+----5----+----6 0 0 0 0 0 0 *********************************** FB2 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use data_0_cmp_eq0005/data_0_cmp_eq0005_D2 1 0 /\2 2 FB2_1 (b) (b) reset 1 0 0 4 FB2_2 99 GSR/I/O I data_0_cmp_eq0004/data_0_cmp_eq0004_D2 1 0 \/4 0 FB2_3 (b) (b) (unused) 0 0 \/5 0 FB2_4 (b) (b) ram_rom_adr<14> 11 9<- \/3 0 FB2_5 1 GTS/I/O O ram_rom_adr<13> 18 13<- 0 0 FB2_6 2 GTS/I/O O (unused) 0 0 /\5 0 FB2_7 (b) (b) turbo_speed_out 3 3<- /\5 0 FB2_8 3 GTS/I/O O data_0_cmp_eq0002/data_0_cmp_eq0002_D2 1 0 /\3 1 FB2_9 4 GTS/I/O I data_0_cmp_eq0001/data_0_cmp_eq0001_D2 1 0 0 4 FB2_10 (b) (b) data_0_cmp_eq0000/data_0_cmp_eq0000_D2 1 0 0 4 FB2_11 6 I/O I ram_rom_adr<9> 1 0 0 4 FB2_12 7 I/O O $OpTx$FX_DC$670 1 0 0 4 FB2_13 (b) (b) $OpTx$FX_DC$583 1 0 0 4 FB2_14 8 I/O I ram_bank_1 3 0 0 2 FB2_15 9 I/O I happy_a12 3 0 0 2 FB2_16 (b) (b) $OpTx$INV$575 4 0 \/1 0 FB2_17 10 I/O I N27/N27_D2 8 3<- 0 0 FB2_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$578 15: adr<15> 29: happy_a12 2: $OpTx$FX_DC$598 16: adr<1> 30: ms_speed_select 3: N120/N120_D2 17: adr<2> 31: ram_bank_0 4: N177/N177_D2 18: adr<3> 32: ram_bank_1 5: riot_ready_inout.PIN 19: adr<4> 33: reset 6: data<1>.PIN 20: adr<5> 34: reset_sync 7: N27/N27_D2 21: adr<6> 35: rom_bank_c000_0 8: N28/N28_D2 22: adr<7> 36: rom_bank_c000_1 9: adr<0> 23: adr<8> 37: rom_base_bank_1 10: adr<10> 24: adr<9> 38: rom_base_bank_2 11: adr<11> 25: floppy_mode<0> 39: rom_source_is_ram 12: adr<12> 26: floppy_mode<1> 40: rw 13: adr<13> 27: floppy_mode<2> 41: turbo_speed_in 14: adr<14> 28: floppy_mode<3> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs data_0_cmp_eq0005/data_0_cmp_eq0005_D2 ........XXXXXXXXXXXXXXXX.......................... 16 reset .................................X................ 1 data_0_cmp_eq0004/data_0_cmp_eq0004_D2 ........XXXXXXXXXXXXXXXX.......................... 16 ram_rom_adr<14> X.....X.....XXX.........XXXX...X...X.XX........... 13 ram_rom_adr<13> X.X......XXXXXX......X..XXXX..X...X.X.XX.......... 18 turbo_speed_out X...X...................XXXX.X..........X......... 8 data_0_cmp_eq0002/data_0_cmp_eq0002_D2 ........XXXXXXXXXXXXXXXX.......................... 16 data_0_cmp_eq0001/data_0_cmp_eq0001_D2 ........XXXXXXXXXXXXXXXX.......................... 16 data_0_cmp_eq0000/data_0_cmp_eq0000_D2 ........XXXXXXXXXXXXXXXX.......................... 16 ram_rom_adr<9> .X.....................X.......................... 2 $OpTx$FX_DC$670 X.......XXXXXXXXXXXXXXXX..XX...................... 19 $OpTx$FX_DC$583 ........XXXXXXXXXXXXXXXX.......................... 16 ram_bank_1 X....X.X...XXXX.........XXXX...XX......X.......... 14 happy_a12 ........XXX.X..XXXXXXXXXXXXXX...X................. 19 $OpTx$INV$575 ...X....XXXXXXXXXXXXXXXX.......................... 17 N27/N27_D2 .X.......XXXXXX.........XXXX...........X.......... 12 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB3 *********************************** Number of function block inputs used/remaining: 45/9 Number of signals used by logic mapping into function block: 45 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use track_hi<5> 5 3<- /\3 0 FB3_1 (b) (b) i2c_clk_and0000/i2c_clk_and0000_D2 1 0 /\3 1 FB3_2 23 GCK/I/O I data_0_cmp_eq0006/data_0_cmp_eq0006_D2 1 0 0 4 FB3_3 (b) (b) $OpTx$FX_DC$626 1 0 \/1 3 FB3_4 (b) (b) io_1050 7 2<- 0 0 FB3_5 24 I/O O ram_bank_5 2 0 /\1 2 FB3_6 25 I/O I track_hi<1> 3 0 0 2 FB3_7 (b) (b) N3/N3_D2 3 0 \/2 0 FB3_8 27 GCK/I/O GCK/I ram_rom_adr<11> 9 4<- 0 0 FB3_9 28 I/O O N2/N2_D2 3 0 /\2 0 FB3_10 (b) (b) ram_rom_adr<8> 8 3<- 0 0 FB3_11 29 I/O O $OpTx$FX_DC$627 3 1<- /\3 0 FB3_12 30 I/O I track_hi<4> 4 0 /\1 0 FB3_13 (b) (b) density<1> 4 0 0 1 FB3_14 32 I/O I (unused) 0 0 \/5 0 FB3_15 33 I/O I (unused) 0 0 \/5 0 FB3_16 (b) (b) ram_rom_adr<12> 23 18<- 0 0 FB3_17 34 I/O O (unused) 0 0 /\5 0 FB3_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$578 16: adr<14> 31: floppy_mode<0> 2: $OpTx$FX_DC$594 17: adr<15> 32: floppy_mode<1> 3: $OpTx$FX_DC$598 18: adr<1> 33: floppy_mode<2> 4: $OpTx$FX_DC$627 19: adr<2> 34: floppy_mode<3> 5: N120/N120_D2 20: adr<3> 35: happy_a12 6: data<5>.PIN 21: adr<4> 36: ram_bank_5 7: data<4>.PIN 22: adr<5> 37: reset 8: data<1>.PIN 23: adr<6> 38: rom_base_bank_0 9: N28/N28_D2 24: adr<7> 39: rom_source_is_ram 10: N3/N3_D2 25: adr<8> 40: rw 11: adr<0> 26: adr<9> 41: track_hi<1> 12: adr<10> 27: archiver_a11 42: track_hi<4> 13: adr<11> 28: check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 43: track_hi<5> 14: adr<12> 29: data<7>.PIN 44: turbo_rom_adr<11> 15: adr<13> 30: density<1> 45: turbo_rom_adr<12> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs track_hi<5> .X...XX..XX....XXX............XXXX..X..X..X....... 15 i2c_clk_and0000/i2c_clk_and0000_D2 ...........XXXXXX.XXXXXXXX........................ 14 data_0_cmp_eq0006/data_0_cmp_eq0006_D2 ..........XXXXXXXXXXXXXXXX........................ 16 $OpTx$FX_DC$626 ...........XXXXXX..XXXXXXX.............X.......... 14 io_1050 ...........XXX.........X.X.X..XXXX................ 10 ram_bank_5 X....X..X....XXXX...............XX.XX..X.......... 12 track_hi<1> .X.....X.XX....XXX...............X..X..XX......... 11 N3/N3_D2 ..........X...XXXX............XXXX.....X.......... 10 ram_rom_adr<11> ..X........XXX............X...XXXX.....X...X...... 11 N2/N2_D2 ..........X...XXXX............XXXX.....X.......... 10 ram_rom_adr<8> ....X......X.X.........XXX....XXXX................ 10 $OpTx$FX_DC$627 ..........X...XXXX............XXXX.....X.......... 10 track_hi<4> .X....X..XX....XXX............XXXX..X..X.X........ 14 density<1> .X.X...X..X....XXX..........XXXXXX..X..X.......... 15 ram_rom_adr<12> X.X........XXXXXX.............XXXXX..XXX....X..... 17 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB4 *********************************** Number of function block inputs used/remaining: 47/7 Number of signals used by logic mapping into function block: 47 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use track_lo<0> 7 4<- /\2 0 FB4_1 (b) (b) track_lo_out<3> 1 0 /\4 0 FB4_2 87 I/O O ram_bank_4 3 0 0 2 FB4_3 (b) (b) ram_bank_3 3 0 0 2 FB4_4 (b) (b) track_lo_out<2> 1 0 0 4 FB4_5 89 I/O O track_lo_out<1> 1 0 0 4 FB4_6 90 I/O O ram_bank_2 3 0 0 2 FB4_7 (b) (b) track_lo_out<0> 1 0 \/3 1 FB4_8 91 I/O O ram_bank_0 3 3<- \/5 0 FB4_9 92 I/O I track_lo<4> 6 5<- \/4 0 FB4_10 (b) (b) track_lo<1> 7 4<- \/2 0 FB4_11 93 I/O I ram_rom_adr<18> 7 2<- 0 0 FB4_12 94 I/O O (unused) 0 0 \/3 2 FB4_13 (b) (b) ram_rom_adr<17> 6 3<- \/2 0 FB4_14 95 I/O O ram_rom_adr<16> 6 2<- \/1 0 FB4_15 96 I/O O (unused) 0 0 \/5 0 FB4_16 (b) (b) ram_rom_adr<15> 18 13<- 0 0 FB4_17 97 I/O O (unused) 0 0 /\5 0 FB4_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$578 17: adr<13> 33: rom_bank_c000_3 2: $OpTx$FX_DC$594 18: adr<14> 34: rom_bank_c000_4 3: N120/N120_D2 19: adr<15> 35: rom_bank_c000_5 4: N2/N2_D2 20: adr<1> 36: rom_bank_c000_enable<0> 5: data<4>.PIN 21: adr<7> 37: rom_base_bank_3 6: data<3>.PIN 22: floppy_mode<0> 38: rom_base_bank_4 7: data<2>.PIN 23: floppy_mode<1> 39: rom_base_bank_5 8: data<1>.PIN 24: floppy_mode<2> 40: rom_base_bank_6 9: data<0>.PIN 25: floppy_mode<3> 41: rom_source_is_ram 10: N27/N27_D2 26: ram_bank_0 42: rw 11: N28/N28_D2 27: ram_bank_2 43: track_lo<0> 12: N76/N76_D2 28: ram_bank_3 44: track_lo<1> 13: adr<0> 29: ram_bank_4 45: track_lo<2> 14: adr<10> 30: ram_bank_5 46: track_lo<3> 15: adr<11> 31: reset 47: track_lo<4> 16: adr<12> 32: rom_bank_c000_2 Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs track_lo<0> .X.X.XXXX...X....XXX.XXXX.....X..........XX....... 17 track_lo_out<3> .............................................X.... 1 ram_bank_4 X...X.....X....XXXX..XXXX...X.X..........X........ 14 ram_bank_3 X....X....X....XXXX..XXXX..X..X..........X........ 14 track_lo_out<2> ............................................X..... 1 track_lo_out<1> ...........................................X...... 1 ram_bank_2 X.....X...X....XXXX..XXXX.X...X..........X........ 14 track_lo_out<0> ..........................................X....... 1 ram_bank_0 X.......X.X....XXXX..XXXXX....X..........X........ 14 track_lo<4> .X.XXXXXX...X....XXX.XXXX.....X..........X....X... 18 track_lo<1> .X.X.XXXX...X....XXX.XXXX.....X..........X.X...... 17 ram_rom_adr<18> X........X.X....XXX..XXXX....X....XX...XX......... 15 ram_rom_adr<17> X........X.X....XXX..XXXX...X....X.X..X.X......... 15 ram_rom_adr<16> X........X.X....XXX..XXXX..X....X..X.X..X......... 15 ram_rom_adr<15> X.X..........XXXXXX.XXXXX.X....X...XX...XX........ 19 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB5 *********************************** Number of function block inputs used/remaining: 41/13 Number of signals used by logic mapping into function block: 41 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 2 0 0 3 FB5_1 (b) (b) floppy_mode<3> 2 0 0 3 FB5_2 35 I/O I floppy_mode<2> 2 0 0 3 FB5_3 (b) (b) $OpTx$INV$574 2 0 0 3 FB5_4 (b) (b) $OpTx$FX_DC$598 2 0 0 3 FB5_5 36 I/O I ms_write_enable 3 0 0 2 FB5_6 37 I/O I ms_speed_select 3 0 0 2 FB5_7 (b) (b) i2c_data 3 0 0 2 FB5_8 39 I/O I i2c_clk 3 0 0 2 FB5_9 40 I/O I floppy_mode<1> 3 0 \/1 1 FB5_10 (b) (b) ram_rom_adr<10> 3 1<- \/3 0 FB5_11 41 I/O O ram_ce 21 16<- 0 0 FB5_12 42 I/O O (unused) 0 0 /\5 0 FB5_13 (b) (b) (unused) 0 0 /\5 0 FB5_14 43 I/O I d7_ram_rom 2 0 /\3 0 FB5_15 46 I/O I/O floppy_mode<0> 3 0 0 2 FB5_16 (b) (b) ram_rom_oe 1 0 0 4 FB5_17 49 I/O O data_7_mux0000/data_7_mux0000_TRST 4 0 0 1 FB5_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$578 15: adr<11> 29: floppy_mode<3> 2: $OpTx$FX_DC$583 16: adr<12> 30: i2c_clk 3: $OpTx$FX_DC$598 17: adr<13> 31: i2c_clk_and0000/i2c_clk_and0000_D2 4: $OpTx$FX_DC$626 18: adr<14> 32: i2c_data 5: $OpTx$FX_DC$652 19: adr<15> 33: ms_speed_select 6: $OpTx$INV$575 20: adr<1> 34: ms_write_enable 7: N120/N120_D2 21: adr<2> 35: phi2 8: d7_ram_rom.PIN 22: adr<7> 36: ram_bank_3 9: data<3>.PIN 23: data<7>.PIN 37: ram_bank_4 10: data<2>.PIN 24: data_0_cmp_eq0005/data_0_cmp_eq0005_D2 38: reset 11: data<1>.PIN 25: data_0_cmp_eq0006/data_0_cmp_eq0006_D2 39: rom_bank_c000_enable<0> 12: data<0>.PIN 26: floppy_mode<0> 40: rom_source_is_ram 13: adr<0> 27: floppy_mode<1> 41: rw 14: adr<10> 28: floppy_mode<2> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 .......X......XX.........XXXX........X............ 8 floppy_mode<3> XX......X..................XX........X............ 6 floppy_mode<2> XX.......X.................XX........X............ 6 $OpTx$INV$574 X..X..........XX....X....XXXX..................... 9 $OpTx$FX_DC$598 ......X......X.X.....X...XXXX..................... 8 ms_write_enable X..........X............X..XX....X...X..X......... 8 ms_speed_select X..........X...........X...XX...X....X..X......... 8 i2c_data X..................X.......XX.XX.....X..X......... 8 i2c_clk X...........X..............XXXX......X..X......... 8 floppy_mode<1> XX........X...............XXX........X............ 7 ram_rom_adr<10> ......X......X.X.....X...XXXX..................... 8 ram_ce ..X..........XXXXXX......XXXX......XX.XXX......... 16 d7_ram_rom ....X.................X...........X.....X......... 4 floppy_mode<0> XX.........X.............X.XX........X............ 7 ram_rom_oe ..................................X.....X......... 2 data_7_mux0000/data_7_mux0000_TRST X...XX........XX.........XXXX.X...X.....X......... 12 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 *********************************** FB6 *********************************** Number of function block inputs used/remaining: 30/24 Number of signals used by logic mapping into function block: 30 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use reset_sync 1 0 0 4 FB6_1 (b) (b) track_hi_out<5> 1 0 0 4 FB6_2 74 I/O O N120/N120_D2 1 0 0 4 FB6_3 (b) (b) rom_source_is_ram 2 0 0 3 FB6_4 (b) (b) track_hi_out<4> 1 0 0 4 FB6_5 76 I/O O track_hi_out<3> 1 0 0 4 FB6_6 77 I/O O rom_base_bank_6 2 0 0 3 FB6_7 (b) (b) track_hi_out<2> 1 0 0 4 FB6_8 78 I/O O track_hi_out<1> 1 0 0 4 FB6_9 79 I/O O rom_base_bank_5 2 0 0 3 FB6_10 (b) (b) rom_base_bank_4 2 0 0 3 FB6_11 80 I/O I track_hi_out<0> 1 0 0 4 FB6_12 81 I/O O rom_base_bank_3 2 0 0 3 FB6_13 (b) (b) track_lo_out<6> 1 0 0 4 FB6_14 82 I/O O track_lo_out<5> 1 0 0 4 FB6_15 85 I/O O rom_base_bank_2 2 0 0 3 FB6_16 (b) (b) track_lo_out<4> 1 0 0 4 FB6_17 86 I/O O rom_base_bank_1 2 0 0 3 FB6_18 (b) (b) Signals Used by Logic in Function Block 1: data<6>.PIN 11: data<7>.PIN 21: rom_source_is_ram 2: data<5>.PIN 12: reset 22: track_hi<0> 3: data<4>.PIN 13: reset_in 23: track_hi<1> 4: data<3>.PIN 14: rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 24: track_hi<2> 5: data<2>.PIN 15: rom_base_bank_1 25: track_hi<3> 6: data<1>.PIN 16: rom_base_bank_2 26: track_hi<4> 7: adr<10> 17: rom_base_bank_3 27: track_hi<5> 8: adr<7> 18: rom_base_bank_4 28: track_lo<4> 9: adr<9> 19: rom_base_bank_5 29: track_lo<5> 10: check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 20: rom_base_bank_6 30: track_lo<6> Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs reset_sync ............X........................... 1 track_hi_out<5> ..........................X............. 1 N120/N120_D2 ......XXXX.............................. 4 rom_source_is_ram ..........XX.X......X................... 4 track_hi_out<4> .........................X.............. 1 track_hi_out<3> ........................X............... 1 rom_base_bank_6 X..........X.X.....X.................... 4 track_hi_out<2> .......................X................ 1 track_hi_out<1> ......................X................. 1 rom_base_bank_5 .X.........X.X....X..................... 4 rom_base_bank_4 ..X........X.X...X...................... 4 track_hi_out<0> .....................X.................. 1 rom_base_bank_3 ...X.......X.X..X....................... 4 track_lo_out<6> .............................X.......... 1 track_lo_out<5> ............................X........... 1 rom_base_bank_2 ....X......X.X.X........................ 4 track_lo_out<4> ...........................X............ 1 rom_base_bank_1 .....X.....X.XX......................... 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB7 *********************************** Number of function block inputs used/remaining: 39/15 Number of signals used by logic mapping into function block: 39 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use turbo_rom_adr<12> 2 0 0 3 FB7_1 (b) (b) ram_rom_we 1 0 0 4 FB7_2 50 I/O O turbo_rom_adr<11> 2 0 0 3 FB7_3 (b) (b) rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 2 0 0 3 FB7_4 (b) (b) fdc_write_out 3 0 0 2 FB7_5 52 I/O O rom_base_bank_0 2 0 0 3 FB7_6 53 I/O I rom_bank_c000_enable<0> 2 0 0 3 FB7_7 (b) (b) rom_bank_c000_5 2 0 0 3 FB7_8 54 I/O I riot_ready_inout 2 0 0 3 FB7_9 55 I/O I/O rom_bank_c000_4 2 0 0 3 FB7_10 (b) (b) cfg_led 2 0 0 3 FB7_11 56 I/O O rom_bank_c000_3 2 0 0 3 FB7_12 58 I/O I rom_bank_c000_2 2 0 0 3 FB7_13 (b) (b) i2c_clk_pin 1 0 0 4 FB7_14 59 I/O O i2c_data_pin 1 0 0 4 FB7_15 60 I/O I/O rom_bank_c000_1 2 0 0 3 FB7_16 (b) (b) rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2 0 0 3 FB7_17 61 I/O I rom_bank_c000_0 2 0 0 3 FB7_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$578 14: data_0_cmp_eq0002/data_0_cmp_eq0002_D2 27: rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 2: $OpTx$FX_DC$670 15: fdc_write_in 28: rom_bank_c000_1 3: data<6>.PIN 16: floppy_mode<0> 29: rom_bank_c000_2 4: data<5>.PIN 17: floppy_mode<1> 30: rom_bank_c000_3 5: data<4>.PIN 18: floppy_mode<2> 31: rom_bank_c000_4 6: data<3>.PIN 19: floppy_mode<3> 32: rom_bank_c000_5 7: data<2>.PIN 20: i2c_clk 33: rom_bank_c000_enable<0> 8: data<1>.PIN 21: i2c_data 34: rom_base_bank_0 9: data<0>.PIN 22: ms_write_enable 35: rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 10: archiver_a11 23: phi2 36: rw 11: cfg_led 24: reset 37: turbo_rom_adr<11> 12: data<7>.PIN 25: riot_ready_in 38: turbo_rom_adr<12> 13: data_0_cmp_eq0001/data_0_cmp_eq0001_D2 26: rom_bank_c000_0 39: turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 Signal 1 2 3 4 FB Name 0----+----0----+----0----+----0----+----0 Inputs turbo_rom_adr<12> ...X...................X.............XX. 4 ram_rom_we ......................X............X.... 2 turbo_rom_adr<11> ..X.X..................X............X.X. 5 rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 X............X...XX....X................ 5 fdc_write_out X........X....X.XXX..X.................. 7 rom_base_bank_0 ........X..............X.........XX..... 4 rom_bank_c000_enable<0> ...........X...........X..X.....X....... 4 rom_bank_c000_5 ...X...................X..X....X........ 4 riot_ready_inout ...............XXXX.....X............... 5 rom_bank_c000_4 ....X..................X..X...X......... 4 cfg_led .X......X.X............X................ 4 rom_bank_c000_3 .....X.................X..X..X.......... 4 rom_bank_c000_2 ......X................X..X.X........... 4 i2c_clk_pin ...................X.................... 1 i2c_data_pin ....................X................... 1 rom_bank_c000_1 .......X...............X..XX............ 4 rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 X...........X....XX....X...........X.... 6 rom_bank_c000_0 ........X..............X.XX............. 4 0----+----1----+----2----+----3----+----4 0 0 0 0 *********************************** FB8 *********************************** Number of function block inputs used/remaining: 44/10 Number of signals used by logic mapping into function block: 44 Signal Total Imp Exp Unused Loc Pin Pin Pin Name Pt Pt Pt Pt # Type Use track_hi<6> 4 1<- /\2 0 FB8_1 (b) (b) track_hi<3> 4 0 /\1 0 FB8_2 63 I/O I track_hi<2> 4 0 0 1 FB8_3 (b) (b) track_hi<0> 4 0 \/1 0 FB8_4 (b) (b) centronics_data 4 1<- \/2 0 FB8_5 64 I/O O centronics_strobe 8 3<- 0 0 FB8_6 65 I/O O density<2> 4 0 /\1 0 FB8_7 (b) (b) centronics_clk 4 0 0 1 FB8_8 66 I/O O summer 2 0 0 3 FB8_9 67 I/O O density<0> 5 0 0 0 FB8_10 (b) (b) density_out<2> 1 0 0 4 FB8_11 68 I/O O density_out<1> 1 0 \/1 3 FB8_12 70 I/O O track_lo<6> 6 1<- 0 0 FB8_13 (b) (b) density_out<0> 1 0 0 4 FB8_14 71 I/O O track_hi_out<6> 1 0 \/3 1 FB8_15 72 I/O O track_lo<2> 6 3<- \/2 0 FB8_16 (b) (b) track_lo<5> 7 2<- 0 0 FB8_17 73 I/O I track_lo<3> 7 2<- 0 0 FB8_18 (b) (b) Signals Used by Logic in Function Block 1: $OpTx$FX_DC$578 16: adr<0> 31: floppy_mode<0> 2: $OpTx$FX_DC$594 17: adr<11> 32: floppy_mode<1> 3: $OpTx$FX_DC$626 18: adr<12> 33: floppy_mode<2> 4: $OpTx$FX_DC$627 19: adr<13> 34: floppy_mode<3> 5: $OpTx$INV$574 20: adr<14> 35: reset 6: N2/N2_D2 21: adr<15> 36: rw 7: d7_ram_rom.PIN 22: adr<1> 37: track_hi<0> 8: data<6>.PIN 23: adr<2> 38: track_hi<2> 9: data<5>.PIN 24: centronics_clk 39: track_hi<3> 10: data<4>.PIN 25: centronics_data 40: track_hi<6> 11: data<3>.PIN 26: centronics_strobe 41: track_lo<2> 12: data<2>.PIN 27: data<7>.PIN 42: track_lo<3> 13: data<1>.PIN 28: density<0> 43: track_lo<5> 14: data<0>.PIN 29: density<1> 44: track_lo<6> 15: N3/N3_D2 30: density<2> Signal 1 2 3 4 5 FB Name 0----+----0----+----0----+----0----+----0----+----0 Inputs track_hi<6> .X.....XX.....XX...XXX........XXXXXX...X.......... 15 track_hi<3> .X......XXX...XX...XXX........XXXXXX..X........... 16 track_hi<2> .X......XX.X..XX...XXX........XXXXXX.X............ 16 track_hi<0> .X......XX...XXX...XXX........XXXXXXX............. 16 centronics_data X.X.X.X.X.......XX...XX.X.....XXXXX............... 15 centronics_strobe ..X...XX.......XXX...XX..X....XXXXX............... 14 density<2> .X.X...X...X...X...XXX.......XXXXXXX.............. 15 centronics_clk X.X.X.X..X.....XXX....XX......XXXXX............... 15 summer ...............X..XXXX........XXXXXX.............. 11 density<0> .X.X...X.....X.X...XXX....XX..XXXXXX.............. 16 density_out<2> .............................X.................... 1 density_out<1> ............................X..................... 1 track_lo<6> .X...X.X..XXXX.X...XXX........XXXXXX.......X...... 18 density_out<0> ...........................X...................... 1 track_hi_out<6> .......................................X.......... 1 track_lo<2> .X...X....XXXX.X...XXX........XXXXXX....X......... 17 track_lo<5> .X...X..X.XXXX.X...XXX........XXXXXX......X....... 18 track_lo<3> .X...X....XXXX.X...XXX........XXXXXX.....X........ 17 0----+----1----+----2----+----3----+----4----+----5 0 0 0 0 0 ******************************* Equations ******************************** ********** Mapped Logic ********** $OpTx$FX_DC$578 <= floppy_mode(0) XOR $OpTx$FX_DC$578 <= floppy_mode(1); $OpTx$FX_DC$583 <= (NOT adr(6) AND NOT adr(3) AND adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); $OpTx$FX_DC$594 <= ((NOT floppy_mode(2) AND NOT adr(13)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0))); $OpTx$FX_DC$598 <= ((N120/N120_D2) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND NOT adr(10) AND NOT adr(7))); $OpTx$FX_DC$626 <= (NOT adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(5) AND adr(4) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); $OpTx$FX_DC$627 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(0) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1))); $OpTx$FX_DC$652 <= ((NOT ram_ce) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT rom_source_is_ram AND rw AND adr(12)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15) AND NOT $OpTx$FX_DC$578) OR (NOT floppy_mode(3) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15) AND adr(12)) OR (NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(12)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(0) AND NOT rom_source_is_ram AND rw AND adr(12)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(12) AND adr(11))); $OpTx$FX_DC$670 <= (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(6) AND adr(3) AND adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7) AND NOT $OpTx$FX_DC$578); $OpTx$INV$574 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(2) AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$626) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(12) AND NOT adr(11))); $OpTx$INV$575 <= ((NOT N177/N177_D2) OR (NOT adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)) OR (NOT adr(6) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)) OR (adr(6) AND adr(3) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7))); N120/N120_D2 <= (NOT adr(10) AND NOT adr(9) AND NOT adr(7) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2); N177/N177_D2 <= (NOT data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND NOT $OpTx$FX_DC$583); N2/N2_D2 <= ((NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(0) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1))); N27/N27_D2 <= (($OpTx$FX_DC$598) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND NOT adr(14) AND NOT adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND NOT adr(10) AND adr(11)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND NOT adr(14) AND adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT rw AND adr(12)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND adr(12) AND NOT adr(11)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT adr(14) AND adr(15))); N28/N28_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(12)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(12))); N3/N3_D2 <= ((NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(0) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1))); N76/N76_D2 <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND NOT $OpTx$FX_DC$578)); FDCPE_centronics_clk: FDCPE port map (centronics_clk,centronics_clk_D,NOT phi2,'0','0'); centronics_clk_D <= ((NOT reset) OR (centronics_clk AND NOT $OpTx$INV$574) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(0) AND NOT adr(2) AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$626) OR (d7_ram_rom.PIN AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(12) AND NOT adr(11) AND data(4).PIN)); FDCPE_centronics_data: FDCPE port map (centronics_data,centronics_data_D,NOT phi2,'0','0'); centronics_data_D <= ((NOT reset) OR (d7_ram_rom.PIN AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(12) AND NOT adr(11) AND data(5).PIN) OR (centronics_data AND NOT $OpTx$INV$574) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(1) AND NOT adr(2) AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$626)); FTCPE_centronics_strobe: FTCPE port map (centronics_strobe,centronics_strobe_T,NOT phi2,'0','0'); centronics_strobe_T <= ((d7_ram_rom.PIN AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(12) AND NOT adr(11) AND centronics_strobe AND reset AND NOT data(6).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(0) AND NOT adr(1) AND adr(2) AND centronics_strobe AND reset AND $OpTx$FX_DC$626) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT adr(0) AND NOT adr(1) AND adr(2) AND centronics_strobe AND reset AND $OpTx$FX_DC$626) OR (NOT centronics_strobe AND NOT reset) OR (NOT d7_ram_rom.PIN AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(12) AND NOT adr(11) AND NOT centronics_strobe) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(12) AND NOT adr(11) AND NOT centronics_strobe AND data(6).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND adr(0) AND NOT adr(1) AND adr(2) AND NOT centronics_strobe AND $OpTx$FX_DC$626) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND adr(0) AND NOT adr(1) AND adr(2) AND NOT centronics_strobe AND $OpTx$FX_DC$626)); FDCPE_cfg_led: FDCPE port map (cfg_led,cfg_led_D,NOT phi2,'0','0'); cfg_led_D <= ((data(0).PIN AND reset AND $OpTx$FX_DC$670) OR (cfg_led AND reset AND NOT $OpTx$FX_DC$670)); check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2 <= ((NOT floppy_mode(3) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT adr(14) AND NOT adr(15)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(12)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND NOT adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT adr(12)) OR (NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(13) AND NOT adr(14) AND NOT adr(15))); d7_ram_rom_I <= data(7).PIN; d7_ram_rom <= d7_ram_rom_I when d7_ram_rom_OE = '1' else 'Z'; d7_ram_rom_OE <= (phi2 AND NOT rw AND $OpTx$FX_DC$652); data_I(0) <= ((rom_base_bank_0 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (floppy_mode(0) AND $OpTx$FX_DC$583 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (ms_speed_select AND NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND NOT $OpTx$FX_DC$583 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (ms_write_enable AND data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND NOT $OpTx$FX_DC$583 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (turbo_speed_in AND NOT data_0_cmp_eq0006/data_0_cmp_eq0006_D2 AND NOT data_0_cmp_eq0004/data_0_cmp_eq0004_D2 AND NOT data_0_cmp_eq0005/data_0_cmp_eq0005_D2 AND NOT $OpTx$FX_DC$583 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_enc_a AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_0 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2)); data(0) <= data_I(0) when data_OE(0) = '1' else 'Z'; data_OE(0) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575); data_I(1) <= ((floppy_mode(1) AND $OpTx$FX_DC$583 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (archiver_a11 AND N177/N177_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_enc_b AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_bank_c000_1 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_1 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(1) <= data_I(1) when data_OE(1) = '1' else 'Z'; data_OE(1) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575); data_I(2) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_2 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_3 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (floppy_mode(2) AND $OpTx$FX_DC$583 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (riot_ready_in AND N177/N177_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_enc_ok AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(2) <= data_I(2) when data_OE(2) = '1' else 'Z'; data_OE(2) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575); data_I(3) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_3 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (floppy_mode(3) AND $OpTx$FX_DC$583 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (fdc_write_in AND N177/N177_D2 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND NOT data_0_cmp_eq0002/data_0_cmp_eq0002_D2) OR (cfg_sw1 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_4 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_3 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(3) <= data_I(3) when data_OE(3) = '1' else 'Z'; data_OE(3) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575); data_I(4) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_4 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (cfg_sw2 AND data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_5 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_4 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(4) <= data_I(4) when data_OE(4) = '1' else 'Z'; data_OE(4) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575); data_I(5) <= ((rom_bank_c000_enable(0) AND rom_bank_c000_5 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (NOT rom_bank_c000_enable(0) AND rom_base_bank_6 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2) OR (rom_base_bank_5 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); data(5) <= data_I(5) when data_OE(5) = '1' else 'Z'; data_OE(5) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575); data_I(6) <= (rom_base_bank_6 AND NOT data_0_cmp_eq0001/data_0_cmp_eq0001_D2 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2); data(6) <= data_I(6) when data_OE(6) = '1' else 'Z'; data_OE(6) <= (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575); data_I(7) <= ((N177/N177_D2.EXP) OR (d7_ram_rom.PIN AND floppy_mode(2) AND floppy_mode(1)) OR (d7_ram_rom.PIN AND floppy_mode(2) AND NOT floppy_mode(0)) OR (d7_ram_rom.PIN AND NOT floppy_mode(2) AND $OpTx$FX_DC$578) OR (d7_ram_rom.PIN AND NOT floppy_mode(2) AND NOT $OpTx$INV$575 AND NOT i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND i2c_data_pin.PIN AND NOT $OpTx$FX_DC$578 AND NOT data_0_cmp_eq0000/data_0_cmp_eq0000_D2 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (d7_ram_rom.PIN AND floppy_mode(3)) OR (d7_ram_rom.PIN AND floppy_mode(2) AND NOT rw) OR (d7_ram_rom.PIN AND floppy_mode(2) AND NOT adr(12)) OR (d7_ram_rom.PIN AND floppy_mode(2) AND adr(11))); data(7) <= data_I(7) when data_OE(7) = '1' else 'Z'; data_OE(7) <= data_7_mux0000/data_7_mux0000_TRST; data_0_cmp_eq0000/data_0_cmp_eq0000_D2 <= (NOT adr(6) AND adr(3) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); data_0_cmp_eq0001/data_0_cmp_eq0001_D2 <= (NOT adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); data_0_cmp_eq0002/data_0_cmp_eq0002_D2 <= (NOT adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); data_0_cmp_eq0004/data_0_cmp_eq0004_D2 <= (NOT adr(6) AND adr(3) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND adr(5) AND NOT adr(1) AND adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); data_0_cmp_eq0005/data_0_cmp_eq0005_D2 <= (adr(6) AND NOT adr(3) AND NOT adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); data_0_cmp_eq0006/data_0_cmp_eq0006_D2 <= (adr(6) AND NOT adr(3) AND adr(0) AND adr(13) AND adr(14) AND NOT adr(15) AND NOT adr(5) AND NOT adr(1) AND NOT adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); data_7_mux0000/data_7_mux0000_TRST <= ((phi2 AND rw AND $OpTx$FX_DC$652) OR (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND $OpTx$INV$575) OR (phi2 AND NOT floppy_mode(3) AND NOT floppy_mode(2) AND rw AND NOT $OpTx$FX_DC$578 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (phi2 AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND rw AND adr(12) AND NOT adr(11))); FDCPE_density0: FDCPE port map (density(0),density_D(0),NOT phi2,'0','0'); density_D(0) <= ((NOT reset) OR (density(0) AND NOT $OpTx$FX_DC$627) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(7).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(6).PIN) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$594)); FDCPE_density1: FDCPE port map (density(1),density_D(1),NOT phi2,'0','0'); density_D(1) <= ((NOT reset) OR (density(1) AND NOT $OpTx$FX_DC$627) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(7).PIN) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND NOT data(1).PIN AND $OpTx$FX_DC$594)); FDCPE_density2: FDCPE port map (density(2),density_D(2),NOT phi2,'0','0'); density_D(2) <= ((NOT reset) OR (density(2) AND NOT $OpTx$FX_DC$627) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(6).PIN) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND NOT data(2).PIN AND $OpTx$FX_DC$594)); density_out_I(0) <= '0'; density_out(0) <= density_out_I(0) when density_out_OE(0) = '1' else 'Z'; density_out_OE(0) <= NOT density(0); density_out_I(1) <= '0'; density_out(1) <= density_out_I(1) when density_out_OE(1) = '1' else 'Z'; density_out_OE(1) <= NOT density(1); density_out_I(2) <= '0'; density_out(2) <= density_out_I(2) when density_out_OE(2) = '1' else 'Z'; density_out_OE(2) <= NOT density(2); fdc_write_out <= NOT (((NOT fdc_write_in) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT ms_write_enable AND NOT $OpTx$FX_DC$578) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT archiver_a11 AND NOT $OpTx$FX_DC$578))); FTCPE_floppy_mode0: FTCPE port map (floppy_mode(0),floppy_mode_T(0),NOT phi2,'0','0'); floppy_mode_T(0) <= ((floppy_mode(0) AND NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND NOT data(0).PIN AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$583) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(0) AND data(0).PIN AND reset AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$583)); FTCPE_floppy_mode1: FTCPE port map (floppy_mode(1),floppy_mode_T(1),NOT phi2,'0','0'); floppy_mode_T(1) <= ((floppy_mode(1) AND NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT data(1).PIN AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$583) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND data(1).PIN AND reset AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$583)); FDCPE_floppy_mode2: FDCPE port map (floppy_mode(2),floppy_mode_D(2),NOT phi2,'0','0'); floppy_mode_D(2) <= ((floppy_mode(2) AND reset) OR (NOT floppy_mode(3) AND data(2).PIN AND reset AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$583)); FDCPE_floppy_mode3: FDCPE port map (floppy_mode(3),floppy_mode_D(3),NOT phi2,'0','0'); floppy_mode_D(3) <= ((floppy_mode(3) AND reset) OR (NOT floppy_mode(2) AND data(3).PIN AND reset AND NOT $OpTx$FX_DC$578 AND $OpTx$FX_DC$583)); FTCPE_happy_a12: FTCPE port map (happy_a12,happy_a12_T,NOT phi2,'0','0'); happy_a12_T <= ((NOT happy_a12 AND NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(6) AND adr(3) AND adr(0) AND adr(13) AND adr(5) AND NOT adr(1) AND adr(4) AND NOT happy_a12 AND NOT adr(2) AND adr(10) AND adr(11) AND adr(9) AND adr(8) AND adr(7)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(6) AND adr(3) AND NOT adr(0) AND adr(13) AND adr(5) AND NOT adr(1) AND adr(4) AND happy_a12 AND NOT adr(2) AND adr(10) AND adr(11) AND adr(9) AND adr(8) AND adr(7) AND reset)); FTCPE_i2c_clk: FTCPE port map (i2c_clk,i2c_clk_T,NOT phi2,'0','0'); i2c_clk_T <= ((NOT i2c_clk AND NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(0) AND NOT rw AND NOT i2c_clk AND NOT $OpTx$FX_DC$578 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(0) AND NOT rw AND i2c_clk AND reset AND NOT $OpTx$FX_DC$578 AND i2c_clk_and0000/i2c_clk_and0000_D2)); i2c_clk_and0000/i2c_clk_and0000_D2 <= (NOT adr(6) AND NOT adr(3) AND adr(13) AND adr(14) AND NOT adr(15) AND adr(5) AND NOT adr(4) AND NOT adr(2) AND adr(12) AND NOT adr(10) AND NOT adr(11) AND NOT adr(9) AND NOT adr(8) AND NOT adr(7)); i2c_clk_pin_I <= '0'; i2c_clk_pin <= i2c_clk_pin_I when i2c_clk_pin_OE = '1' else 'Z'; i2c_clk_pin_OE <= NOT i2c_clk; FTCPE_i2c_data: FTCPE port map (i2c_data,i2c_data_T,NOT phi2,'0','0'); i2c_data_T <= ((NOT i2c_data AND NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND adr(1) AND NOT i2c_data AND NOT $OpTx$FX_DC$578 AND i2c_clk_and0000/i2c_clk_and0000_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND NOT adr(1) AND i2c_data AND reset AND NOT $OpTx$FX_DC$578 AND i2c_clk_and0000/i2c_clk_and0000_D2)); i2c_data_pin_I <= '0'; i2c_data_pin <= i2c_data_pin_I when i2c_data_pin_OE = '1' else 'Z'; i2c_data_pin_OE <= NOT i2c_data; io_1050 <= NOT (((NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND adr(7)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND NOT adr(11) AND adr(7)) OR (adr(10) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (adr(9) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (adr(7) AND check_1050_6810_access_mux0001/check_1050_6810_access_mux0001_D2) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND adr(10)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND adr(10)))); FTCPE_ms_speed_select: FTCPE port map (ms_speed_select,ms_speed_select_T,NOT phi2,'0','0'); ms_speed_select_T <= ((NOT ms_speed_select AND NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND NOT ms_speed_select AND data(0).PIN AND NOT $OpTx$FX_DC$578 AND data_0_cmp_eq0005/data_0_cmp_eq0005_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND ms_speed_select AND NOT data(0).PIN AND reset AND NOT $OpTx$FX_DC$578 AND data_0_cmp_eq0005/data_0_cmp_eq0005_D2)); FTCPE_ms_write_enable: FTCPE port map (ms_write_enable,ms_write_enable_T,NOT phi2,'0','0'); ms_write_enable_T <= ((NOT ms_write_enable AND NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND NOT ms_write_enable AND data(0).PIN AND NOT $OpTx$FX_DC$578 AND data_0_cmp_eq0006/data_0_cmp_eq0006_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND ms_write_enable AND NOT data(0).PIN AND reset AND NOT $OpTx$FX_DC$578 AND data_0_cmp_eq0006/data_0_cmp_eq0006_D2)); FDCPE_ram_bank_0: FDCPE port map (ram_bank_0,ram_bank_0_D,NOT phi2,'0','0'); ram_bank_0_D <= ((reset AND ram_bank_0 AND NOT N28/N28_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(0).PIN AND reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(12) AND data(0).PIN AND reset AND NOT $OpTx$FX_DC$578)); FDCPE_ram_bank_1: FDCPE port map (ram_bank_1,ram_bank_1_D,NOT phi2,'0','0'); ram_bank_1_D <= ((reset AND ram_bank_1 AND NOT N28/N28_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT adr(12) AND reset AND NOT $OpTx$FX_DC$578)); FDCPE_ram_bank_2: FDCPE port map (ram_bank_2,ram_bank_2_D,NOT phi2,'0','0'); ram_bank_2_D <= ((reset AND ram_bank_2 AND NOT N28/N28_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(2).PIN AND reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(2).PIN AND NOT adr(12) AND reset AND NOT $OpTx$FX_DC$578)); FDCPE_ram_bank_3: FDCPE port map (ram_bank_3,ram_bank_3_D,NOT phi2,'0','0'); ram_bank_3_D <= ((reset AND ram_bank_3 AND NOT N28/N28_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND NOT adr(12) AND reset AND NOT $OpTx$FX_DC$578)); FDCPE_ram_bank_4: FDCPE port map (ram_bank_4,ram_bank_4_D,NOT phi2,'0','0'); ram_bank_4_D <= ((reset AND ram_bank_4 AND NOT N28/N28_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND reset AND data(4).PIN) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(12) AND reset AND data(4).PIN AND NOT $OpTx$FX_DC$578)); FDCPE_ram_bank_5: FDCPE port map (ram_bank_5,ram_bank_5_D,NOT phi2,'0','0'); ram_bank_5_D <= ((reset AND ram_bank_5 AND NOT N28/N28_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(12) AND data(5).PIN AND reset AND NOT $OpTx$FX_DC$578)); ram_ce <= NOT ((($OpTx$FX_DC$598) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT rw AND adr(12)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(0) AND rom_source_is_ram AND rw AND adr(12)) OR (EXP25_.EXP) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(13) AND adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND adr(12) AND NOT adr(11)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15) AND NOT ram_bank_3) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT adr(14) AND adr(15) AND NOT ram_bank_4) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(14) AND adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND rom_source_is_ram AND rw AND adr(12)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND rom_source_is_ram AND rw AND adr(12)))); ram_rom_adr(8) <= ((floppy_mode(3) AND adr(8) AND NOT N120/N120_D2) OR (NOT floppy_mode(2) AND adr(8) AND NOT N120/N120_D2) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND NOT adr(10) AND adr(9) AND NOT adr(7) AND NOT N120/N120_D2) OR (NOT floppy_mode(1) AND adr(8) AND NOT N120/N120_D2) OR (NOT floppy_mode(0) AND adr(8) AND NOT N120/N120_D2) OR (adr(12) AND adr(8) AND NOT N120/N120_D2) OR (adr(10) AND adr(8) AND NOT N120/N120_D2) OR (adr(8) AND adr(7) AND NOT N120/N120_D2)); ram_rom_adr(9) <= NOT ((NOT adr(9) AND NOT $OpTx$FX_DC$598)); ram_rom_adr(10) <= ((adr(10)) OR (N120/N120_D2) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND NOT adr(7))); ram_rom_adr(11) <= NOT (((floppy_mode(3) AND NOT adr(11) AND NOT $OpTx$FX_DC$598) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT rw AND adr(12) AND NOT $OpTx$FX_DC$598) OR (floppy_mode(1) AND NOT adr(11) AND NOT $OpTx$FX_DC$598) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND adr(12) AND NOT archiver_a11 AND NOT $OpTx$FX_DC$598) OR (NOT floppy_mode(2) AND NOT adr(11) AND NOT $OpTx$FX_DC$598) OR (NOT floppy_mode(0) AND NOT adr(11) AND NOT $OpTx$FX_DC$598) OR (NOT adr(12) AND NOT adr(11) AND NOT $OpTx$FX_DC$598) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT adr(12) AND NOT adr(10) AND NOT $OpTx$FX_DC$598) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT turbo_rom_adr(11) AND adr(12) AND NOT $OpTx$FX_DC$598))); ram_rom_adr(12) <= (($OpTx$FX_DC$598) OR (EXP18_.EXP) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(12)) OR (floppy_mode(3) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND NOT adr(13) AND rom_base_bank_0) OR (floppy_mode(3) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0 AND adr(10)) OR (floppy_mode(3) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0 AND NOT adr(11)) OR (track_hi(5).EXP) OR (floppy_mode(3) AND floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_0) OR (floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_0 AND NOT $OpTx$FX_DC$578) OR (NOT floppy_mode(3) AND NOT floppy_mode(1) AND floppy_mode(0) AND turbo_rom_adr(12) AND adr(12)) OR (floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_0 AND NOT adr(12)) OR (floppy_mode(3) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0 AND NOT adr(12)) OR (floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_0) OR (NOT floppy_mode(2) AND floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_0 AND adr(12)) OR (floppy_mode(3) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(14) AND NOT adr(15) AND rom_base_bank_0) OR (floppy_mode(3) AND NOT rom_source_is_ram AND rw AND rom_base_bank_0 AND adr(12) AND adr(11)) OR (floppy_mode(3) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND NOT adr(14) AND adr(15) AND rom_base_bank_0)); ram_rom_adr(13) <= ((floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_1 AND NOT N120/N120_D2) OR (floppy_mode(2) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_1 AND NOT N120/N120_D2) OR (floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_1 AND adr(10) AND NOT N120/N120_D2) OR (turbo_speed_out_OBUF.EXP) OR (floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_1 AND adr(7) AND NOT N120/N120_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND NOT adr(14) AND adr(15) AND NOT N120/N120_D2) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(13) AND adr(15) AND NOT N120/N120_D2) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(14) AND adr(15) AND NOT N120/N120_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(14) AND adr(15) AND rom_bank_c000_0 AND NOT $OpTx$FX_DC$578 AND NOT N120/N120_D2) OR (floppy_mode(3) AND NOT rom_source_is_ram AND rom_base_bank_1 AND NOT N120/N120_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND adr(14) AND NOT N120/N120_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND NOT adr(15) AND NOT N120/N120_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(13) AND ram_bank_0 AND NOT N120/N120_D2) OR (floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_1 AND adr(12) AND NOT N120/N120_D2)); ram_rom_adr(14) <= ((N27/N27_D2) OR (data_0_cmp_eq0004/data_0_cmp_eq0004_D2.EXP) OR (NOT rom_source_is_ram AND NOT adr(15) AND rom_base_bank_2) OR (floppy_mode(3) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rom_base_bank_2) OR (floppy_mode(3) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND rom_base_bank_2) OR (floppy_mode(3) AND NOT rom_source_is_ram AND adr(13) AND rom_base_bank_2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(15) AND NOT $OpTx$FX_DC$578) OR (floppy_mode(2) AND NOT rom_source_is_ram AND rom_base_bank_2)); ram_rom_adr(15) <= NOT (((N120/N120_D2) OR (ram_rom_adr_16_OBUF.EXP) OR (NOT rom_bank_c000_enable(0) AND NOT rom_source_is_ram AND adr(14) AND NOT rom_base_bank_3) OR (NOT rom_source_is_ram AND adr(13) AND adr(14) AND NOT rom_base_bank_3) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(13) AND NOT adr(14) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND NOT ram_bank_2) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(14) AND adr(15)) OR (track_lo(0).EXP) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(13) AND adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT rw AND adr(12)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND adr(12) AND NOT adr(11)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT adr(14) AND adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(13) AND NOT adr(14) AND NOT adr(15)) OR (floppy_mode(3) AND NOT rom_source_is_ram AND NOT rom_base_bank_3) OR (floppy_mode(2) AND NOT rom_source_is_ram AND NOT rom_base_bank_3) OR (NOT rom_source_is_ram AND NOT adr(15) AND NOT rom_base_bank_3) OR (NOT rom_source_is_ram AND adr(14) AND NOT rom_base_bank_3 AND $OpTx$FX_DC$578))); ram_rom_adr(16) <= ((N27/N27_D2) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(13) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_3 AND NOT $OpTx$FX_DC$578) OR (rom_source_is_ram AND NOT N76/N76_D2) OR (rom_base_bank_4 AND NOT N76/N76_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_3)); ram_rom_adr(17) <= ((N27/N27_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT adr(14) AND adr(15) AND ram_bank_4) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(13) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_4 AND NOT $OpTx$FX_DC$578) OR (rom_source_is_ram AND NOT N76/N76_D2) OR (rom_base_bank_5 AND NOT N76/N76_D2)); ram_rom_adr(18) <= ((N27/N27_D2) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT adr(14) AND adr(15) AND ram_bank_5) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(15) AND rom_bank_c000_5 AND NOT $OpTx$FX_DC$578) OR (rom_source_is_ram AND NOT N76/N76_D2) OR (rom_base_bank_6 AND NOT N76/N76_D2) OR (floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(1) AND floppy_mode(0) AND NOT adr(13) AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND floppy_mode(0) AND NOT adr(14) AND adr(15) AND ram_bank_5)); ram_rom_oe <= NOT ((phi2 AND rw)); ram_rom_we <= NOT ((phi2 AND NOT rw)); FDCPE_reset: FDCPE port map (reset,reset_sync,NOT phi2,'0','0'); FDCPE_reset_sync: FDCPE port map (reset_sync,reset_in,NOT phi2,'0','0'); riot_ready_inout_I <= riot_ready_in; riot_ready_inout <= riot_ready_inout_I when riot_ready_inout_OE = '1' else 'Z'; riot_ready_inout_OE <= NOT ((floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0))); FDCPE_rom_bank_c000_0: FDCPE port map (rom_bank_c000_0,rom_bank_c000_0_D,NOT phi2,'0','0'); rom_bank_c000_0_D <= ((rom_bank_c000_0 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(0).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2 <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rw AND NOT $OpTx$FX_DC$578 AND data_0_cmp_eq0001/data_0_cmp_eq0001_D2)); FDCPE_rom_bank_c000_1: FDCPE port map (rom_bank_c000_1,rom_bank_c000_1_D,NOT phi2,'0','0'); rom_bank_c000_1_D <= ((NOT rom_bank_c000_1 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (NOT data(1).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_2: FDCPE port map (rom_bank_c000_2,rom_bank_c000_2_D,NOT phi2,'0','0'); rom_bank_c000_2_D <= ((rom_bank_c000_2 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(2).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_3: FDCPE port map (rom_bank_c000_3,rom_bank_c000_3_D,NOT phi2,'0','0'); rom_bank_c000_3_D <= ((rom_bank_c000_3 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(3).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_4: FDCPE port map (rom_bank_c000_4,rom_bank_c000_4_D,NOT phi2,'0','0'); rom_bank_c000_4_D <= ((rom_bank_c000_4 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (reset AND data(4).PIN AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_5: FDCPE port map (rom_bank_c000_5,rom_bank_c000_5_D,NOT phi2,'0','0'); rom_bank_c000_5_D <= ((rom_bank_c000_5 AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (data(5).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_bank_c000_enable0: FDCPE port map (rom_bank_c000_enable(0),rom_bank_c000_enable_D(0),NOT phi2,'0','0'); rom_bank_c000_enable_D(0) <= ((rom_bank_c000_enable(0) AND NOT rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2) OR (NOT data(7).PIN AND reset AND rom_bank_c000_0__or0000/rom_bank_c000_0__or0000_D2)); FDCPE_rom_base_bank_0: FDCPE port map (rom_base_bank_0,rom_base_bank_0_D,NOT phi2,'0','0'); rom_base_bank_0_D <= ((rom_base_bank_0 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(0).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2 <= ((NOT reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT $OpTx$FX_DC$578 AND data_0_cmp_eq0002/data_0_cmp_eq0002_D2)); FDCPE_rom_base_bank_1: FDCPE port map (rom_base_bank_1,rom_base_bank_1_D,NOT phi2,'0','0'); rom_base_bank_1_D <= ((rom_base_bank_1 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(1).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_2: FDCPE port map (rom_base_bank_2,rom_base_bank_2_D,NOT phi2,'0','0'); rom_base_bank_2_D <= ((rom_base_bank_2 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(2).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_3: FDCPE port map (rom_base_bank_3,rom_base_bank_3_D,NOT phi2,'0','0'); rom_base_bank_3_D <= ((NOT rom_base_bank_3 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(3).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_4: FDCPE port map (rom_base_bank_4,rom_base_bank_4_D,NOT phi2,'0','0'); rom_base_bank_4_D <= ((NOT rom_base_bank_4 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (reset AND NOT data(4).PIN AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_5: FDCPE port map (rom_base_bank_5,rom_base_bank_5_D,NOT phi2,'0','0'); rom_base_bank_5_D <= ((NOT rom_base_bank_5 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (NOT data(5).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FDCPE_rom_base_bank_6: FDCPE port map (rom_base_bank_6,rom_base_bank_6_D,NOT phi2,'0','0'); rom_base_bank_6_D <= ((NOT rom_base_bank_6 AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (reset AND NOT data(6).PIN AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); rom_ce <= NOT (((NOT floppy_mode(3) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND rom_bank_c000_enable(0) AND NOT adr(13) AND adr(14) AND adr(15) AND NOT $OpTx$FX_DC$578) OR (NOT floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15)) OR (NOT floppy_mode(2) AND floppy_mode(1) AND NOT rom_source_is_ram AND adr(13) AND adr(14) AND rw AND adr(15) AND adr(12)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(12)) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(0) AND NOT rom_source_is_ram AND rw AND adr(12)) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT rom_source_is_ram AND adr(14) AND rw AND adr(15)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND NOT rom_source_is_ram AND rw AND adr(12)) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT rom_source_is_ram AND rw AND adr(12) AND adr(11)))); FDCPE_rom_source_is_ram: FDCPE port map (rom_source_is_ram,rom_source_is_ram_D,NOT phi2,'0','0'); rom_source_is_ram_D <= ((rom_source_is_ram AND NOT rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2) OR (data(7).PIN AND reset AND rom_base_bank_0__or0000/rom_base_bank_0__or0000_D2)); FTCPE_summer: FTCPE port map (summer,summer_T,NOT phi2,'0','0'); summer_T <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND adr(0) AND NOT adr(13) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND reset) OR (NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND adr(1) AND reset)); FDCPE_track_hi0: FDCPE port map (track_hi(0),track_hi_D(0),NOT phi2,'0','0'); track_hi_D(0) <= ((NOT reset) OR (track_hi(0) AND NOT N3/N3_D2) OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$594) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND data(4).PIN)); FDCPE_track_hi1: FDCPE port map (track_hi(1),track_hi_D(1),NOT phi2,'0','0'); track_hi_D(1) <= ((NOT reset) OR (track_hi(1) AND NOT N3/N3_D2) OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(1).PIN AND $OpTx$FX_DC$594)); FDCPE_track_hi2: FDCPE port map (track_hi(2),track_hi_D(2),NOT phi2,'0','0'); track_hi_D(2) <= ((NOT reset) OR (track_hi(2) AND NOT N3/N3_D2) OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(2).PIN AND $OpTx$FX_DC$594) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN AND NOT data(4).PIN)); FDCPE_track_hi3: FDCPE port map (track_hi(3),track_hi_D(3),NOT phi2,'0','0'); track_hi_D(3) <= ((NOT reset) OR (track_hi(3) AND NOT N3/N3_D2) OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(3).PIN AND $OpTx$FX_DC$594) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN AND data(4).PIN)); FDCPE_track_hi4: FDCPE port map (track_hi(4),track_hi_D(4),NOT phi2,'0','0'); track_hi_D(4) <= ((NOT reset) OR (track_hi(4) AND NOT N3/N3_D2) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN) OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$594)); FDCPE_track_hi5: FDCPE port map (track_hi(5),track_hi_D(5),NOT phi2,'0','0'); track_hi_D(5) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(5).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(4).PIN) OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$594) OR (track_hi(5) AND NOT N3/N3_D2)); FDCPE_track_hi6: FDCPE port map (track_hi(6),track_hi_D(6),NOT phi2,'0','0'); track_hi_D(6) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(5).PIN) OR (track_hi(6) AND NOT N3/N3_D2) OR (NOT floppy_mode(3) AND adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$594)); track_hi_out_I(0) <= '0'; track_hi_out(0) <= track_hi_out_I(0) when track_hi_out_OE(0) = '1' else 'Z'; track_hi_out_OE(0) <= NOT track_hi(0); track_hi_out_I(1) <= '0'; track_hi_out(1) <= track_hi_out_I(1) when track_hi_out_OE(1) = '1' else 'Z'; track_hi_out_OE(1) <= NOT track_hi(1); track_hi_out_I(2) <= '0'; track_hi_out(2) <= track_hi_out_I(2) when track_hi_out_OE(2) = '1' else 'Z'; track_hi_out_OE(2) <= NOT track_hi(2); track_hi_out_I(3) <= '0'; track_hi_out(3) <= track_hi_out_I(3) when track_hi_out_OE(3) = '1' else 'Z'; track_hi_out_OE(3) <= NOT track_hi(3); track_hi_out_I(4) <= '0'; track_hi_out(4) <= track_hi_out_I(4) when track_hi_out_OE(4) = '1' else 'Z'; track_hi_out_OE(4) <= NOT track_hi(4); track_hi_out_I(5) <= '0'; track_hi_out(5) <= track_hi_out_I(5) when track_hi_out_OE(5) = '1' else 'Z'; track_hi_out_OE(5) <= NOT track_hi(5); track_hi_out_I(6) <= '0'; track_hi_out(6) <= track_hi_out_I(6) when track_hi_out_OE(6) = '1' else 'Z'; track_hi_out_OE(6) <= NOT track_hi(6); FDCPE_track_lo0: FDCPE port map (track_lo(0),track_lo_D(0),NOT phi2,'0','0'); track_lo_D(0) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (track_lo(0) AND NOT N2/N2_D2) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(0).PIN AND $OpTx$FX_DC$594)); FDCPE_track_lo1: FDCPE port map (track_lo(1),track_lo_D(1),NOT phi2,'0','0'); track_lo_D(1) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND data(0).PIN) OR (track_lo(1) AND NOT N2/N2_D2) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(1).PIN AND $OpTx$FX_DC$594)); FDCPE_track_lo2: FDCPE port map (track_lo(2),track_lo_D(2),NOT phi2,'0','0'); track_lo_D(2) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND data(2).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN) OR (track_lo(2) AND NOT N2/N2_D2) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(2).PIN AND $OpTx$FX_DC$594)); FDCPE_track_lo3: FDCPE port map (track_lo(3),track_lo_D(3),NOT phi2,'0','0'); track_lo_D(3) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(3).PIN AND NOT data(2).PIN AND NOT data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (track_lo(3) AND NOT N2/N2_D2) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(3).PIN AND $OpTx$FX_DC$594) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN)); FDCPE_track_lo4: FDCPE port map (track_lo(4),track_lo_D(4),NOT phi2,'0','0'); track_lo_D(4) <= ((NOT reset) OR (track_lo(4) AND NOT N2/N2_D2) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(4).PIN AND $OpTx$FX_DC$594) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND data(2).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(2).PIN AND data(0).PIN)); FDCPE_track_lo5: FDCPE port map (track_lo(5),track_lo_D(5),NOT phi2,'0','0'); track_lo_D(5) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(3).PIN AND NOT data(2).PIN AND data(0).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND data(0).PIN) OR (track_lo(5) AND NOT N2/N2_D2) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(5).PIN AND $OpTx$FX_DC$594) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND data(0).PIN)); FDCPE_track_lo6: FDCPE port map (track_lo(6),track_lo_D(6),NOT phi2,'0','0'); track_lo_D(6) <= ((NOT reset) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND data(3).PIN AND data(2).PIN AND NOT data(0).PIN) OR (track_lo(6) AND NOT N2/N2_D2) OR (NOT floppy_mode(3) AND NOT adr(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT adr(1) AND NOT data(6).PIN AND $OpTx$FX_DC$594) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND NOT data(1).PIN AND NOT data(3).PIN AND NOT data(2).PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND floppy_mode(1) AND NOT floppy_mode(0) AND adr(14) AND NOT rw AND NOT adr(15) AND data(1).PIN AND NOT data(3).PIN AND data(2).PIN AND data(0).PIN)); track_lo_out_I(0) <= '0'; track_lo_out(0) <= track_lo_out_I(0) when track_lo_out_OE(0) = '1' else 'Z'; track_lo_out_OE(0) <= NOT track_lo(0); track_lo_out_I(1) <= '0'; track_lo_out(1) <= track_lo_out_I(1) when track_lo_out_OE(1) = '1' else 'Z'; track_lo_out_OE(1) <= NOT track_lo(1); track_lo_out_I(2) <= '0'; track_lo_out(2) <= track_lo_out_I(2) when track_lo_out_OE(2) = '1' else 'Z'; track_lo_out_OE(2) <= NOT track_lo(2); track_lo_out_I(3) <= '0'; track_lo_out(3) <= track_lo_out_I(3) when track_lo_out_OE(3) = '1' else 'Z'; track_lo_out_OE(3) <= NOT track_lo(3); track_lo_out_I(4) <= '0'; track_lo_out(4) <= track_lo_out_I(4) when track_lo_out_OE(4) = '1' else 'Z'; track_lo_out_OE(4) <= NOT track_lo(4); track_lo_out_I(5) <= '0'; track_lo_out(5) <= track_lo_out_I(5) when track_lo_out_OE(5) = '1' else 'Z'; track_lo_out_OE(5) <= NOT track_lo(5); track_lo_out_I(6) <= '0'; track_lo_out(6) <= track_lo_out_I(6) when track_lo_out_OE(6) = '1' else 'Z'; track_lo_out_OE(6) <= NOT track_lo(6); FDCPE_turbo_rom_adr11: FDCPE port map (turbo_rom_adr(11),turbo_rom_adr_D(11),NOT phi2,'0','0'); turbo_rom_adr_D(11) <= ((NOT turbo_rom_adr(11) AND NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2) OR (reset AND NOT data(6).PIN AND NOT data(4).PIN AND turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2)); FDCPE_turbo_rom_adr12: FDCPE port map (turbo_rom_adr(12),turbo_rom_adr_D(12),NOT phi2,'0','0'); turbo_rom_adr_D(12) <= ((NOT turbo_rom_adr(12) AND NOT turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2) OR (data(5).PIN AND reset AND turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2)); turbo_rom_adr_11__or0001/turbo_rom_adr_11__or0001_D2 <= ((NOT reset) OR (NOT d7_ram_rom.PIN AND NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND adr(12) AND NOT adr(11))); turbo_speed_out <= ((NOT floppy_mode(3) AND NOT floppy_mode(2) AND NOT ms_speed_select AND NOT $OpTx$FX_DC$578) OR (floppy_mode(3) AND NOT floppy_mode(2) AND NOT floppy_mode(1) AND NOT floppy_mode(0) AND NOT riot_ready_inout.PIN) OR (NOT floppy_mode(3) AND floppy_mode(2) AND NOT floppy_mode(1) AND floppy_mode(0) AND turbo_speed_in)); Register Legend: FDCPE (Q,D,C,CLR,PRE,CE); FTCPE (Q,D,C,CLR,PRE,CE); LDCP (Q,D,G,CLR,PRE); ****************************** Device Pin Out ***************************** Device : XC95144XL-10-TQ100 -------------------------------------------------- /100 98 96 94 92 90 88 86 84 82 80 78 76 \ | 99 97 95 93 91 89 87 85 83 81 79 77 | | 1 75 | | 2 74 | | 3 73 | | 4 72 | | 5 71 | | 6 70 | | 7 69 | | 8 68 | | 9 67 | | 10 66 | | 11 65 | | 12 64 | | 13 XC95144XL-10-TQ100 63 | | 14 62 | | 15 61 | | 16 60 | | 17 59 | | 18 58 | | 19 57 | | 20 56 | | 21 55 | | 22 54 | | 23 53 | | 24 52 | | 25 51 | | 27 29 31 33 35 37 39 41 43 45 47 49 | \26 28 30 32 34 36 38 40 42 44 46 48 50 / -------------------------------------------------- Pin Signal Pin Signal No. Name No. Name 1 ram_rom_adr<14> 51 VCC 2 ram_rom_adr<13> 52 fdc_write_out 3 turbo_speed_out 53 archiver_a11 4 turbo_speed_in 54 fdc_write_in 5 VCC 55 riot_ready_inout 6 adr<5> 56 cfg_led 7 ram_rom_adr<9> 57 VCC 8 adr<4> 58 riot_ready_in 9 adr<3> 59 i2c_clk_pin 10 adr<2> 60 i2c_data_pin 11 adr<1> 61 cfg_sw2 12 rom_ce 62 GND 13 adr<0> 63 centronics_busy 14 data<0> 64 centronics_data 15 data<2> 65 centronics_strobe 16 data<1> 66 centronics_clk 17 data<6> 67 summer 18 data<5> 68 density_out<2> 19 data<4> 69 GND 20 data<3> 70 density_out<1> 21 GND 71 density_out<0> 22 data<7> 72 track_hi_out<6> 23 rw 73 cfg_enc_ok 24 io_1050 74 track_hi_out<5> 25 adr<6> 75 GND 26 VCC 76 track_hi_out<4> 27 phi2 77 track_hi_out<3> 28 ram_rom_adr<11> 78 track_hi_out<2> 29 ram_rom_adr<8> 79 track_hi_out<1> 30 adr<7> 80 cfg_sw1 31 GND 81 track_hi_out<0> 32 adr<8> 82 track_lo_out<6> 33 adr<9> 83 TDO 34 ram_rom_adr<12> 84 GND 35 adr<10> 85 track_lo_out<5> 36 adr<11> 86 track_lo_out<4> 37 adr<13> 87 track_lo_out<3> 38 VCC 88 VCC 39 adr<14> 89 track_lo_out<2> 40 adr<15> 90 track_lo_out<1> 41 ram_rom_adr<10> 91 track_lo_out<0> 42 ram_ce 92 cfg_enc_a 43 adr<12> 93 cfg_enc_b 44 GND 94 ram_rom_adr<18> 45 TDI 95 ram_rom_adr<17> 46 d7_ram_rom 96 ram_rom_adr<16> 47 TMS 97 ram_rom_adr<15> 48 TCK 98 VCC 49 ram_rom_oe 99 reset_in 50 ram_rom_we 100 GND Legend : NC = Not Connected, unbonded pin PGND = Unused I/O configured as additional Ground pin TIE = Unused I/O floating -- must tie to VCC, GND or other signal KPR = Unused I/O with weak keeper (leave unconnected) VCC = Dedicated Power Pin GND = Dedicated Ground Pin TDI = Test Data In, JTAG pin TDO = Test Data Out, JTAG pin TCK = Test Clock, JTAG pin TMS = Test Mode Select, JTAG pin PROHIBITED = User reserved pin **************************** Compiler Options **************************** Following is a list of all global compiler options used by the fitter run. Device(s) Specified : xc95144xl-10-TQ100 Optimization Method : DENSITY Multi-Level Logic Optimization : ON Ignore Timing Specifications : OFF Default Register Power Up Value : LOW Keep User Location Constraints : ON What-You-See-Is-What-You-Get : OFF Exhaustive Fitting : ON Keep Unused Inputs : OFF Slew Rate : SLOW Power Mode : LOW Ground on Unused IOs : OFF Set I/O Pin Termination : KEEPER Global Clock Optimization : ON Global Set/Reset Optimization : ON Global Ouput Enable Optimization : ON Input Limit : 21 Pterm Limit : 23